Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same

ABSTRACT

Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

CROSS REFERENCES TO RELATED APPLICATIONS

This application claims priority under 25 U.S.C. §119(e) to U.S.Provisional Patent Application No. 61/088,828, filed Aug. 14, 2008,entitled “Nonvolatile Nanotube Programmable Logic Devices and aNonvolatile Nanotube Field Programmable Gate Array Using Same.”

This application is related to the following applications, the entirecontents of which are incorporated herein by reference in theirentirety:

-   -   U.S. patent application No. ______, filed concurrently herewith,        entitled NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A        NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME;    -   U.S. patent application No. ______, filed concurrently herewith,        entitled NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A        NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME;    -   U.S. patent application No. ______, filed concurrently herewith,        entitled NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A        NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME;    -   U.S. patent application No. ______, filed concurrently herewith,        entitled NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A        NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME;    -   U.S. patent application No. ______, filed concurrently herewith,        entitled NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A        NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME;    -   U.S. patent application Ser. No. 11/280,786, filed on Nov. 15,        2005, entitled TWO-TERMINAL NANOTUBE DEVICES AND SYSTEMS AND        METHODS OF MAKING SAME;    -   U.S. patent application Ser. No. 11/835,583, filed on Aug. 8,        2007, entitled LATCH CIRCUITS AND OPERATION CIRCUITS HAVING        SCALABLE NONVOLATILE NANOTUBE SWITCHES AS ELECTRONIC FUSE        REPLACEMENT ELEMENTS;    -   U.S. patent application Ser. No. 11/835,651, filed on Aug. 8,        2007, entitled NONVOLATILE NANOTUBE DIODES AND NONVOLATILE        NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING        SAME.    -   U.S. patent application Ser. No. 12/486,602, filed on Jun. 17,        2009, entitled NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE        TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME.

TECHNICAL FIELD

The present application is generally related to the field of fieldprogrammable devices (FPDs), also referred to as programmable logicdevices (PLDs), and, more specifically, to logic circuits formed fromnanotube devices.

BACKGROUND Discussion of Related Art

Field programmable devices (FPDs) have grown rapidly because integratedcircuits for a wide variety of product applications in a competitiveenvironment require fast time-to-market for new designs and low (orzero) non-recurring engineering cost (NRE) and low fabrication cost. Lowpower is a requirement for most applications as is portability soconservation of battery power is a requirement and nonvolatile operationis advantageous. Also, integration levels (more function) are increasingrapidly as is the requirement for high performance chips with largelogic capacity and field programmability that are in-circuitprogrammable (in-place in the package without requiring sockets). Fieldprogrammable devices (FPDs) are also sometimes referred to asprogrammable logic devices (PLDs) and the terms FPD and PLD are usedinterchangeably throughout the application.

What is needed in logic design is fast time to market. Lower costs arealso important hence more function in smaller chips. Higher performanceand lower power are especially important in battery poweredapplications. Field programmable logic chips are required for fast timeto market. What is needed are configurable (programmable) logicfunctions and efficient programmable wiring that can be configured(programmed) multiple times in chips mounted on a board. Programmableswitches must be small in size and nonvolatile to enable efficientwiring architectures for implementing configurable (programmable) logicfunctions and be compatible with and easily integrated in CMOStechnologies. Programmable switches must be easy to use and compatiblewith high performance applications. Programmable switches must enablefine-tuning of logic timing for optimum performance.

Overview of Field Programmable Devices

Block diagram 100 illustrated in FIG. 1 shows simple programmable logicdevices (SPLDs) with a smaller number of equivalent logic gates withthousands or tens of thousands of equivalent logic gates; complexprogrammable logic devices (CPLDs) that combine multiple SPLDs withprogrammable wiring (routing) for a higher number of equivalent logicgates such as tens to hundreds of thousands of equivalent logic gates;and field programmable gate arrays (FPGAs) with a large number ofequivalent logic gates in the range of millions to tens of million ofequivalent logic gates for example and into the hundreds of millions ofequivalent logic gates for denser scaled future FPGA chips. A briefdiscussion of field programmable devices is provided in the sectionsthat follow.

Simple Programmable Logic Devices (SPLDs)

Programmable read-only memories (PROMs) were the first chips to enableuser-programmability of the bits in an array. Such chips were used tostore code for system startup (BIOS), algorithms, and other functionsfor example. Simple logic functions can also be performed using PROMs inwhich address lines can be used as logic circuit inputs and data linesas outputs. However, logic functions typically do not require manyproduct terms but a PROM contains a full decoder for its address inputs.Thus, PROMs are an inefficient architecture for programmable logicfunction and are rarely used for this purpose and are therefore notincluded in block diagram 100.

The first SPLD device developed for implementing a field-programmablelogic array (FPLA) or PLA for short consisted of two arrays for storingtwo levels of equivalent logic gates. A first AND array (or AND-plane)is structured such that any of the AND array inputs or complements ofthe inputs can be AND'ed together and each AND-array output correspondsto any product term of inputs to the AND array. These product termoutputs of the AND array become inputs to a second OR array. OR arrayoutputs can be configured to produce any logical sum of any of theproduct terms (AND-array outputs) and implements logic functions insum-of-products form. The PLA architecture is far better for generatinglogic functions than a PROM because both the AND and OR array terms canhave many inputs.

FIG. 2 illustrates a schematic of PLA 200 including programmable ANDarray 210 and programmable OR array 220. Inputs 225 to input drivers 230result in logic functions A, B·C, . . . , D_(C) logic inputs toprogrammable AND array 210. Programmable AND array 210 forms productterms based on the inputs and on the state of nonvolatile bits at theintersection of input lines A, B·C, . . . , D_(C) and provides productterms PT₁, PT₂, . . . , PT_(M) as inputs to Programmable OR array 220.Programmable OR array 220 forms sum-of-products (or product terms)outputs O₁, O₂, . . . , O_(N) based on product terms inputs and thestate of nonvolatile bits at the intersection of product terms PT₁, PT₂,. . . , PT_(M) and OR array output lines O₁, O₂, . . . , O_(N), whichare sent to output drivers 240. Output drivers 240 may be conventionaldrivers, or may include additional logic function such as XOR and mayalso include flip flops such as D-flip flops for example. Output drivers240 drive outputs 245 which is the logic response to inputs 225 based onthe ON or OFF bit states of individual nonvolatile bits in the AND andOR arrays. Also, output driver 240 drives feedback loop 250 whichsupplies output logic response to input drivers 230. Note that some ofthe output lines 245 may be included in feedback loop 250.

In operation, inputs 225 of PLA 200 result in logic outputs 245 based onthe ON and OFF states of devices, such as EPROMs for example, located atthe intersection of input lines such as A, B·C, . . . , D_(C) andproduct term lines PT₁, PT₂, . . . , PT_(M) in electrically programmableAND array 210 and the intersection of PT₁, PT₂, . . . , PT_(M) andoutputs O₁, O₂, . . . , O_(N) in programmable OR array 220. Details ofPLA operation are well known in the literature, for example, C. Mead andLynn Conway, “Introduction to VLSI Systems,” Addison-Wesley PublishingCompany, 1980, pages 79-82.

PLAs such as PLA 200 described further above are the earliest examplesof simple SPLDs introduced in the early 1970's. PLAs using maskprogrammable AND arrays, OR arrays, and feedback loops in a fabricatorwere successfully used by IBM in many applications for over a decade.However, for field programmable PLAs with two memory arrays (memoryplanes) requiring electrically programmable AND and OR arrays, fieldprogrammable PLAs were difficult to manufacture and introducedsignificant propagation delays. To address these problems, simplerprogrammable array logic (PAL) devices were developed which use aprogrammable AND array to realize product terms and then provide saidproduct terms to fixed (non-programmable) OR-gates. To compensate forthe loss of OR array flexibility, product variations were introducedwith different number of inputs and outputs and various sizes ofOR-gates. Field programmable PALs were widely used in digital hardwareimmediately after their introduction and form the basis for more recentand more sophisticated architectures. All small programmable logicdevices (PLDs) such PLAs and PALs are grouped together and referred toas simple field programmable devices (SPDLs) and are typically low costwith high pin-to-pin speed performance as illustrated by block diagram100 in FIG. 1.

FIG. 3 illustrates PAL 300 schematic implementation with an electricallyprogrammable AND array 310 that includes nonvolatile nodes 320 and 325programmed to an ON state, wherein essentially orthogonal programmableAND array lines are electrically coupled, or fused, together (saidelectrical coupling indicated by an open circle). Intersections ofessentially orthogonal programmable AND array lines without circles arein a nonvolatile OFF state, wherein said lines are electricallyisolated. Programmable AND array 310 may be formed usingone-time-programmable EPROM devices for example. Programmable AND array310 may be programmed once in the field. If the logic function needs tobe changed, a new PAL chip is programmed in the field.

PAL 300 inputs A and B form column logic inputs A, A_(C), B, and B_(C)to programmable AND array 310, where A_(C) indicates the complement oflogic variable A and B_(C) indicates the complement of logic variable B.In this specification, the complement of a logic variable such as logicvariable A may be indicated symbolically by A_(C) or A′. Both symbolicalrepresentations for the complement of a logic variable are usedinterchangeably throughout the specification. Feedback loop 330 providesinputs C and D which form programmable AND array column logic inputs C,C_(C), D, and D_(C). Product terms 335-1 and 335-2 form two outputs ofprogrammable AND array 310 and provide inputs to OR logic gate 340. TheOR logic gates are not programmable. Product terms 335-3 and 335-4 formanother two outputs of programmable AND array 310 and provide inputs toOR logic gate 345. OR-gate 340 provides a sum-of-products (orsum-of-product-terms) output to the input of D-flip flop 350 and OR-gate345 provides a sum-of-products output to the input of D-flip flop 355.D-flip flop 350 provides output O₁ which is connected to input C byfeedback loop 330 and D-flip flop 355 provides output O₂ which isconnected to input D by feedback loop 330.

In operation, inputs A and B to PAL 300 result in logic outputs O₁ andO₂ based on the ON and OFF states of devices, such as EPROMs forexample, located at the intersection of input lines and product termlines in electrically programmable AND array 310. Details of PALoperation are well known in the literature and are available in productspecifications.

Complex Programmable Logic Devices (CPLDs)

CPLDs consist of multiple SPLD-like blocks interconnected on a singlechip, typically by a programmable global interconnect matrix resultingin a field programmable logic function that is substantially morepowerful than is possible with even large individual SPLD functions andrepresents a category of programmable logic devices (PLDs) as shown inFIG. 1. The difficulty of increasing capacity of a single SPLDarchitecture is that the array size of the programmable logic-arrays aredriven to large dimensions as the number of inputs increase. Thereforeas technologies are scaled to smaller dimensions and the number oftransistors available on chips increases, it becomes more efficient tolimit the size of SPLDs and to interconnect multiple SPLDs with aprogrammable global interconnect matrix.

FIG. 4 illustrates a schematic of CPLD 400 architecture formed usingfour SPLD functions, SPLD 410, SPLD 420, SPLD 430, and SPLD 440. In oneimplementation, for example, electronically programmable SPLD functionsmay be formed using electronically programmable PALs similar to PAL 300illustrated in FIG. 3. While four interconnected electronicallyprogrammable SPLD functions are illustrated in FIG. 4, dozens ofinterconnected SPLDs may be used to form a large flexible in-circuitprogrammable logic function. All connections between SPLDs, in thisexample PALs similar to PAL 300 described further above with respect toFIG. 3, are routed (wired) through global interconnect matrix 450.

In operation, all communication between SPLD 410 and all other SPLDsused to form CPLD 400 are routed to global interconnect matrix 450 usingwire(s) 410-1 and received from global interconnect matrix 450 usingwire(s) 410-2. All communication between SPLD 420 and all other SPLDsused to form CPLD 400 flow are routed to global interconnect matrix 450using wire(s) 420-1 and received from global interconnect matrix 450using wire(s) 420-2. All communication between SPLD 430 and all otherSPLDs used to form CPLD 400 flow are routed to global interconnectmatrix 450 using wire(s) 430-1 and received from global interconnectmatrix 450 using wire(s) 430-2. And all communication between SPLD 440and all other SPLDs used to form CPLD 400 flow are routed to globalinterconnect matrix 450 using wire(s) 440-1 and received from globalinterconnect matrix 450 using wire(s) 440-2. Multiple inputs and outputs(I/Os) communicate between CPLD 400 and other circuit functions. Sinceall connections are routed through similar paths, time delays can bepredicted which simplifies CPLD design. Buffer circuits (not shown) maybe used as well.

Applications that can exploit wide AND/OR gates and do not require alarge number of flip flops are good candidates for mapping into CPLDs.Control functions such as graphics controllers and some communicationcircuit functions map well into CPLD architectures. In-systemre-programmability and reasonably predictable speed performance aresignificant advantages offered by CPLDs.

Field Programmable Gate Array (FPGA) Logic

FPGAs were invented by Ross Freeman, cofounder of the XilinxCorporation, in 1984 to overcome the limitations of CPLDs. The primarydifferences between CPLDs and FPGAs are due to differences in chiparchitecture. As described further above, CPLD architecture consistsprimarily of programmable sum-of-products logic arrays with a relativelysmall number of clocked registers (D-flip flops for example)interconnected by a global interconnect matrix as illustrated furtherabove by CPLD 400 shown in FIG. 4. CPLDs typically have relatively highlogic-to-interconnect ratios. The result is less architecturalflexibility and smaller logic functions (typically limited to tens tohundreds of thousands of equivalent logic gates) but more predictabletiming delays and greater ease of programming.

FPGA architectures are dominated by interconnects. FPGAs are thereforemuch more flexible in terms of the range of designs that can beimplemented and logic functions in the millions and tens of millions andeventually in the hundreds of millions of equivalent logic gates may berealized. In addition, the added flexibility enables inclusion ofhigher-level embedded functions such adders, multipliers, CPUs, andmemory. The added interconnect (routing) flexibility of FPGAs alsoenables partial reconfiguration such that one portion of an FPGA chipmay be reprogrammed while other portions are running FPGAs that can bereprogrammed while running may enable reconfigurable computing(reconfigurable systems) that reconfigure chip architecture to betterimplement logic tasks. The FPGA's flexibility, ability to support alarge number of equivalent logic gates, and ability to accommodateembedded memory and logic functions are displacing ASICs in manyapplications because of lower non-recurring engineering (NRE) designcosts and faster time-to-market. FPGA architecture is shown in FIG. 1alongside SPLD and CPLD as a stand-alone category of programmable logicdevice architecture.

FPGA architecture and circuit implementations are described in U.S. Pat.Re. 34,363 to Freeman, filed on Jun. 24, 1991, and SRAM memorycontrolled routing switch circuit implementations are described in U.S.Pat. No. 4,670,749 to Freeman, filed on Apr. 13, 1984, the contents ofwhich are incorporated herein by reference in their entirety. FPGA 500(as shown in FIG. 5) schematically illustrates basic concepts taught byFreeman in the above referenced patents by Freeman.

Referring now to FIG. 5, FPGA 500 includes an array of configurable(programmable) logic blocks (CLBs) such as CLB 510 and programmableswitch matrices (PSMs) such as PSM 520. Interconnections between CLBsand PSMs may be relatively short to provide local wiring (such asinterconnect 530) or relatively long to provide global wiring (notshown). A programmable switch (routing) matrix PSM1 interconnecting fourCLB blocks CLB1, CLB2, CLB3, and CLB4 is illustrated in FIG. 5. In thisexample, switch 540, one of the switches in PSM1, may be used tointerconnect CLB1, CLB2, CLB3, and CLB4 in any combination.

CLBs are typically formed by combining look up tables (LUTs) with flipflops and multiplexers as illustrated schematically by CLB 600 in FIG.6. Alternatively, CLBs may be formed by combining combinatorial logicwith flip flops and multiplexers as illustrated by CLB 700 in FIG. 7.

Referring now to FIG. 6, CLB 600 comprises LUT 610 with inputs I₁, . . ., I₂, . . . , I_(N). LUT 610 may be a random access memory (RAM) such asan SRAM, an EPROM, an EEPROM, or a flash memory. A typical LUTconfiguration may be a RAM organized in a 4×4×1 configuration with fourinputs and one output. In this example, the LUT 610 output drives theinput of clocked D-flip flop 620 which in turn drives an input ofmultiplexer (MUX) 630. The LUT 610 output may also drive an input of MUX630 directly. MUX 630 drives (provides) CLB 600 output to terminal O.

Referring now to FIG. 7, CLB 700 includes configurable combinatoriallogic function 710 with inputs I₁, I₂, . . . , I_(N). Configurablecombinatorial logic function 710 may be formed using cascaded transferdevices or random logic blocks such as NAND and NOR functions forexample. Configurable combinatorial logic function 710 formed usingNanoLogic™ functions may also be used as described further below inFIGS. 12 and 14. Typical configurable combinatorial logic function 710may be formed using cascaded transfer devices and configuration controlbits or random logic blocks and configuration control bits. In thisexample, the configurable combinatorial logic function 710 output drivesthe input of clocked D-flip flop 720 which in turn drives an input ofMUX 730. The configurable combinatorial logic function 710 output mayalso drive an input of MUX 730 directly. MUX 730 drives (provides) CLB700 output to terminal O.

The routing flexibility of FPGAs enables a wide variety of functions tobe realized. FIG. 8 illustrates FPGA 800 and shows an example of astatic ram (SRAM) controlled routing of signals between various CLBsenabling an in-circuit programmable logic function. CLB 810 includes anAND gate with inputs I₁ and I₂ and an output O₁ which is provided to PSM812 which includes FET 815 whose ON or OFF states are controlled by SRAM820. FET 815 terminal 1 is connected to output O₁, gate terminal 2 isconnected to SRAM 820, and terminal 3 is connected to wire 825. Wire 825is in turn connected to PSM 828 which includes FET 830 whose ON and OFFstates are controlled by SRAM 820. FET 830 terminal 4 is connected towire 825, gate terminal 5 is connected to SRAM 820, and terminal 6 isconnected to wiring 835. Wiring 835 is also connected to an input of MUX840 which is controlled by SRAM 820. Output O₂ of MUX 840 is connectedto wire 850 which is connected to an input of an AND gate in CLB 855providing an output O₃. A global wire 860 is shown which is not part oflocal wiring.

In operation, output O₁ is applied to terminal 1 of FET 815 with thelogic state (high or low voltage) of gate terminal 2 controlled by SRAM820. If FET 815 is OFF, low gate voltage in this example, then O₁ doesnot propagate along wire 825. If however, FET 815 is ON, high gatevoltage (typically 2.5 volts) in this example, then O₁ propagatesthrough the channel region of FET 815 to terminal 3, and then along wire825 to terminal 4 of FET 830 which is also controlled by SRAM 820. IfFET 830 is in an OFF state, then O₁ does not propagate to terminal 5.However, if FET 830 is in an ON state, then O₁ propagates along wire 835to an input terminal of MUX 840. If MUX 840 is enabled by SRAM 820, thenMUX output O₂ is applied to an input terminal of the AND gate in CLB 855by wire 850. The AND gate output O₃ is also the output of CLB 855.

The use of SRAMs to control wiring in FPGAs as illustrated above withrespect to FIG. 8 and described in U.S. Pat. No. 4,670,749 has theadvantage of compatibility with leading edge CMOS logic processes, isreprogrammable, and supports in-circuit programmability. However, it isthe largest area element having 5 to 6 transistors per cell, requiresexternal loading of bits to define the logic function. Further, in suchSRAM based designs the FPGA is nonfunctional until loading is complete,is volatile, and has relatively low radiation tolerance. In addition,the large SRAM cell size also requires a large number of wiring layersand impacts architecture because the size of the switch is a key factorin determining FPGA architecture.

A very small switch such as a cross point antifuse may also be used forwiring. Such a small switch results in a different architecture and canreduce chip size by approximately 10× relative to an SRAM-based FPGAimplementation. A cross point antifuse is nonvolatile, has very lowcapacitance (1 fF per node for example), is radiation hard, and does notrequire external loading of bits to operate. However, programming suchantifuse based FPGA devices (such as is depicted in FIG. 9) requiresrelatively high voltages such as 5 to 10 volts to ensure breakdown andcurrents in the 5 to 10 mA range. Further such devices areone-time-programmable (OTP) and are difficult to in-circuit program.

FIG. 9 illustrates a schematic of FPGA 900 which includes logic cellssuch as logic cell 910, vertical wiring 920, horizontal wiring 930, andantifuses such as antifuse 940 at each intersection of vertical andhorizontal wires. Such antifuses are typically formed using ONOdielectric-based antifuses or metal-to-metal antifuses. While wiring isshowed in channel regions between logic cells, wiring over logic cells(not shown) may be used to further increase density. I/O circuits suchas I/O 950 interface internal to FPGA 900 circuits and with outputconnections on the chip. FPGA 900 with dense wiring is somewhat similarto ASIC-type layouts although antifuse ON resistance may be in range of25 ohms to several hundred ohms depending on antifuses used. Also, highvoltage circuits (not shown) are included to switch selected cross pointantifuse switches from an OFF to an ON state.

In operation, high voltages typically in the 5-10 volt range with highcurrents in the milliampere range are used to program (change) the crosspoint antifuses from an OFF-to-ON state. Then the logic function can betested. A new chip is required for each logic function and OTPin-circuit programming is difficult. A socket approach can facilitateprogramming of FPGA 900.

SUMMARY

A nonvolatile nanotube programmable devices and the nonvolatile nanotubefield programmable gate array (NFPGA) is provided.

Under certain embodiments, one or more nonvolatile nanotube (NV NT)select circuits are used to store (in a first operation) and laterprovide (in a second operation) one or more control bits to aconventional configurable logic block (CLB) circuit. Said NV NT selectcircuits comprise a pair of nanotube switches and a field effecttransistor (FET). One terminal of each nanotube switch and one terminalof the FET are joined together to form a common node, providing a fourterminal device. During a store operation, the resistance of eachnanotube switch can be set to provide means for nonvolatile storage of asingle control bit. During NFPGA operation, the control bits stored ascorresponding nonvolatile high or low resistance states within each NVNT select circuit can be readily accessed and used to configure the CLBcircuit. This nonvolatile nanotube based CLB system is referred to as anNCLB.

Under certain embodiments, one or more NV NT select circuits are used tostore (in a first operation) and later provide (in a second operation)one or more control bits to a conventional programmable switch matrix(PSM) circuit. During NFPGA operation, the control bits stored ascorresponding nonvolatile high or low resistance states within each NVNT select circuit can be readily accessed and used to configure the PSMcircuit. This nonvolatile nanotube based PSM system is referred to as anNPSM.

Under certain embodiments, a NV NT select circuit is used to store (in afirst operation) and later provide (in a second operation) a control bitto a conventional programmable bidirectional buffer circuit. DuringNFPGA operation, the control bit stored as corresponding nonvolatilehigh or low resistance states within the NV NT select circuit can bereadily accessed and used to configure the direction of the buffercircuit. Additional NV NT select circuits can also be used to eitherenable or disable bypass paths around inverter stages within saidconventional programmable bidirectional buffer circuit, providing meansfor signal inversion through the buffer circuit. Further, additional NVNT select circuits (the nanotube switches of which are configured withnonvolatile resistance values such as to provide a specific resistordivider ratio) can be used to provide programmable supply voltageswithin the buffer circuit, providing means for voltage level translationthrough the buffer circuit. This nonvolatile nanotube based programmablebidirectional buffer system is referred to as an NT BiDi buffer circuit.

Under certain embodiments, a plurality of nonvolatile NRAM™ cells arecombined to form an NRAM™ array, providing means for nonvolatile storageof a plurality of data bits, each data bit corresponding to a uniquecombination of inputs (address) to the array. This NRAM™ array is thenused in place of a conventional (volatile) SRAM array to form aconventional look up table (LUT) circuit. Said NRAM™ cells are comprisedof a single nanotube switch wired in series with a FET, providing athree terminal device which can be used to store (in a first operation)and later recall (in a second operation) a single bit of data. DuringNFPGA operation, the data bits stored within the NRAM array can bereadily accessed and provided to an output stage.

Under certain embodiments, a plurality of nonvolatile NRAM™ cells arecombined to form an NRAM™ array, providing means for nonvolatile storageof a plurality of control bits. This NRAM™ array is then used to store(in a first operation) and later provide (in a second operation) aplurality of control bits to a conventional CLB circuit. During NFPGAoperation, the control bits stored within said NRAM™ array can bereadily accessed and used to configure the CLB circuit. This nonvolatilenanotube based CLB system is referred to as an NCLB.

Under certain embodiments, a plurality of nonvolatile NRAM™ cells arecombined to form an NRAM™ array, providing means for nonvolatile storageof a plurality of control bits. This NRAM™ array is then used to store(in a first operation) and later provide (in a second operation) aplurality of control bits to a conventional PSM circuit. During NFPGAoperation, the control bits stored within said NRAM™ array can bereadily accessed and used to configure the PSM circuit. This nonvolatilenanotube based PSM system is referred to as an NPSM.

Under certain embodiments, a pair of nonvolatile NRAM™ cells is used toprovide nonvolatile backup storage means within a conventional(volatile) SRAM cell. Prior to power loss in such a system, a storeoperation is performed which encodes the bit value stored in thevolatile SRAM cell within each of the NRAM™ cells (a first NRAM™ cellencodes the true bit value, while a second NRAM™ cell encodes thecompliment value). Similarly, a recall operation (typically performedafter power up) is used to load the SRAM cell with the bit value storedwithin the nonvolatile NRAM™ cells.

Under certain embodiments, a plurality of these nanotube supported (or“shadowed”) memory devices—termed nonvolatile nanotube shift registers(NS/Rs), having one nonvolatile nanotube shadow device per shiftregister stage—can be combined to form a nonvolatile nanotubeconfiguration control register (NCCR). Such a device can be used tostore (in a first operation) and later provide (in a second operation) aplurality of control bits to either a conventional CLB or a conventionalPSM circuit, forming a NCLB or a NPSM, respectively.

Under certain embodiments, a plurality of control bits within anonvolatile nanotube based programmable logic element (said control bitssupplied by an NV NT select circuit, NRAM™, NS/R, or some combination orsubcombination of the three) are altered in response to a securityevent. In this way, the configuration of said programmable logicelements is protected from unauthorized access in, for example, anattempt at reverse engineering a device employing nonvolatile nanotubebased programmable logic elements.

Under certain embodiments, programmable supply voltages (programmedusing NV NT select circuits as described further above) are set toprovide precise signal delay values through one or more nonvolatilenanotube based programmable logic elements. As signal rise time througha CMOS circuit, for example, is directly proportional to supply (or“rail”) voltage, precisely selecting a supply voltage for each circuitelement provides means for precisely selecting a delay value throughsaid element. Within this aspect, additional inverter stages may be usedto restore signal levels to predetermined high and low voltages.

Under certain embodiments, programmable supply voltages (programmedusing NV NT select circuits as described further above) provide means toregulate power consumption within a large system of nonvolatile nanotubeprogrammable logic elements, such as, but not limited to, an FPGA.

The nonvolatile nanotube based programmable logic elements can be usedtogether to realize a nonvolatile, rapidly reconfigurable nanotube basedFPGA (NFPGA). Said NFPGA is advantageous because a device can berealized in significantly smaller physical dimensions compared toconventional SRAM based FPGAs of comparable logic density. Said NFPGA isfurther advantageous because it can be readily programmed andreprogrammed in-circuit, in contrast to one-time-programmable (OTP)antifuse or EPROM based FPGAs. Said NFPGA is also advantageous becausesuch a device can be rapidly reconfigured, in whole or in part, duringoperation (in some cases within a single clock cycle).

Accordingly, a nonvolatile nanotube based configurable logic block(NCLB) is disclosed below. It comprises one or more nonvolatile nanotube(NV NT) select circuits and a conventional CLB circuit, wherein said NVNT select circuits are used to store and provide one or moreconfiguration control bits to said conventional CLB circuit.

A nonvolatile nanotube based configurable logic block (NCLB) comprisingan NRAM array is also provided. The array comprises a plurality of NRAMcells, and a conventional CLB circuit, wherein said NRAM array is usedto store and provide one or more configuration control bits to saidconventional CLB circuit.

A nonvolatile nanotube based programmable switch matrix (NPSM) isprovided. It comprises one or more NV NT select circuits and aconventional PSM circuit, wherein said NV NT Select Circuits are used tostore and provide one or more configuration control bits to saidconventional PSM circuit.

A nonvolatile nanotube based programmable switch matrix (NPSM) isprovided. It comprises an NRAM array, said array comprising a pluralityof NRAM cells, and a conventional PSM circuit, wherein said NRAM arrayis used to store and provide one or more configuration control bits tosaid conventional PSM circuit.

A nonvolatile nanotube based programmable bidirectional (NT BiDi) buffercircuit is provided. It comprises a NV NT switch circuit and aconventional bidirectional buffer circuit, wherein said NV NT switch isused to store and provide a control bit to said conventionalbidirectional buffer circuit.

A means within said NT BiDi buffer circuit (through the use of one ormore additional NV NT switch circuits) is provided to invert a datasignal passing through said buffer circuit.

A means within said NT BiDi buffer circuit (through the use of one ormore additional NV NT switch circuits) is provided to level translationof a data signal passing through said buffer circuit.

It is also an object of the present disclosure to provide a nonvolatilenanotube based programmable look up table (LUT) comprising an NRAMarray, said array comprising a plurality of NRAM cells, and an outputstage, wherein said NRAM array, responsive to a plurality of inputsignals, provides a previously stored value for each unique combinationof input values (address) to said output stage.

It is further an object of the present disclosure to provide a nanotubeconfiguration control register (NCCR), said NCCR comprising a pluralityof nonvolatile nanotube shift registers (NS/Rs), which can be used tostore and provide a plurality of control bits within an NCLB or NPSMcircuit.

It is also an object of the present invention to provide means forresponding to a security event (an unauthorized attempt to reverseengineer a device, for example) wherein control bits within one or morenonvolatile nanotube programmable logic devices are altered upondetection of such an event.

It is further an object of the present disclosure to provide means forprecision control of signal delay through one or more nonvolatilenanotube programmable logic devices wherein a programmable supplyvoltage, supplied by one or more NV NT select circuits, is carefullyselected to set a desired signal delay.

It is also an object of the present disclosure to provide means toregulate power consumption within one or more nonvolatile nanotubeprogrammable logic devices by selecting programmable supply voltagessupplied by one or more NV NT select circuits.

It is further an object of the present disclosure to provide annonvolatile nanotube based FPGA (NFPGA) comprising an arrangementnonvolatile nanotube programmable devices selected from a groupconsisting of NCLBs, NPSMs, NT BiDi buffer circuits, NRAM based LUTs,NCCRs.

In one aspect, the present disclosure relates to a programmablenonvolatile nanotube select circuit that can include a firsttwo-terminal nonvolatile nanotube switch and a second two-terminalnonvolatile nanotube switch. Each of the first and second two-terminalnonvolatile nanotube switches can include a first terminal and a secondterminal, wherein the first and second terminals of the firstnonvolatile nanotube switch are in contact with opposite ends of a firstnanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element. The second terminal of the first nonvolatilenanotube switch and the second terminal of the second nonvolatilenanotube switch can share a common node. The programmable nonvolatilenanotube select circuit can also include a field effect transistor (FET)having a drain region, a source region, a channel region positionedbetween the drain and source regions, and a gate node in proximity tothe channel region, wherein the gate node modulates the conductivity ofthe channel region and wherein the drain region of the FET iselectrically coupled to the common node.

In some embodiments, the field effect transistor of the programmablenonvolatile nanotube select circuit is a nanotube field effecttransistor.

In one aspect, the present disclosure relates to a programmable nanotubelogic circuit that can include a programmable nonvolatile nanotubeselect circuit. The programmable nonvolatile nanotube select circuit caninclude a first two-terminal nonvolatile nanotube switch and a secondtwo-terminal nonvolatile nanotube switch. Each of the first and secondtwo-terminal nonvolatile nanotube switches can include a first terminaland a second terminal, wherein the first and second terminals of thefirst nonvolatile nanotube switch are in contact with opposite ends of afirst nanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element. The second terminal of the first nonvolatilenanotube switch and the second terminal of the second nonvolatilenanotube switch can share a common node. The programmable nonvolatilenanotube select circuit can also include a field effect transistor (FET)having a drain region, a source region, a channel region positionedbetween the drain and source regions, and a gate node in proximity tothe channel region, wherein the gate node modulates the conductivity ofthe channel region and wherein the drain region of the FET iselectrically coupled to the common node. The programmable nanotube logiccircuit can also include a Boolean logic circuit that can include atleast one input and an output wherein a first input of the at least oneinputs is electrically coupled to the common node of the programmablenonvolatile nanotube select circuit.

In one aspect, the present disclosure relates to a programmable nanotubecircuit that can include a programmable nonvolatile nanotube selectcircuit. The programmable nonvolatile nanotube select circuit caninclude a first two-terminal nonvolatile nanotube switch and a secondtwo-terminal nonvolatile nanotube switch. Each of the first and secondtwo-terminal nonvolatile nanotube switches can include a first terminaland a second terminal, wherein the first and second terminals of thefirst nonvolatile nanotube switch are in contact with opposite ends of afirst nanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element. The second terminal of the first nonvolatilenanotube switch and the second terminal of the second nonvolatilenanotube switch can share a common node. The programmable nonvolatilenanotube select circuit can also include a field effect transistor (FET)having a drain region, a source region, a channel region positionedbetween the drain and source regions, and a gate node in proximity tothe channel region, wherein the gate node modulates the conductivity ofthe channel region and wherein the drain region of the FET iselectrically coupled to the common node. The programmable nanotubecircuit can also include a transfer device that can include an input, anoutput, and a control terminal wherein the control terminal iselectrically coupled to the common node of the programmable nonvolatilenanotube select circuit to enable transfer of a signal at the input ofthe transfer device to the output of the transfer device.

In one aspect, the present disclosure relates to a nonvolatile nanotubeconfigurable logic circuit that can include a first, second and thirdplurality of input terminals and at least an output terminal, aplurality of programmable nonvolatile nanotube select circuits. Eachprogrammable nonvolatile nanotube select circuit can include a firsttwo-terminal nonvolatile nanotube switch and a second two-terminalnonvolatile nanotube switch. Each of the first and second two-terminalnonvolatile nanotube switches can include a first terminal and a secondterminal, wherein the first and second terminals of the firstnonvolatile nanotube switch are in contact with opposite ends of a firstnanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element. The second terminal of the first nonvolatilenanotube switch and the second terminal of the second nonvolatilenanotube switch can share a common node. The programmable nonvolatilenanotube select circuit can also include a field effect transistor (FET)having a drain region, a source region, a channel region positionedbetween the drain and source regions, and a gate node in proximity tothe channel region, wherein the gate node modulates the conductivity ofthe channel region and wherein the drain region of the FET iselectrically coupled to the common node. The first plurality of inputterminals can be electrically coupled to the first terminals of thenonvolatile nanotube switches and the second plurality of terminals canbe electrically coupled to the gate regions of the nonvolatile nanotubeswitches. A first plurality of transfer devices can be electricallycoupled to the signals on the third plurality of input terminals. Thefirst plurality of transfer devices can also be electrically coupled tothe signals on the common nodes of the nonvolatile nanotube switches. Asecond plurality of transfer devices can be electrically coupled to thecomplementary signals on the third plurality of input terminals, thesecond plurality of transfer devices can also be electrically coupled tothe complementary signals on the common nodes of the nonvolatilenanotube switches, and wherein the signals on the first plurality ofinput terminals can be able to configure the first plurality of transferdevices and the second plurality of transfer devices to implement aplurality of Boolean logic functions at the output terminal.

In one aspect, the present disclosure relates to a nonvolatile nanotubeprogrammable switch matrix that can include a first, second and thirdplurality of terminals, a plurality of programmable nonvolatile nanotubeselect circuits. Each programmable nonvolatile nanotube select circuitcan include a first two-terminal nonvolatile nanotube switch and asecond two-terminal nonvolatile nanotube switch. Each of the first andsecond two-terminal nonvolatile nanotube switches can include a firstterminal and a second terminal, wherein the first and second terminalsof the first nonvolatile nanotube switch are in contact with oppositeends of a first nanotube element and the first and second terminals ofthe second nonvolatile nanotube switch are in contact with opposite endsof a second nanotube element. The second terminal of the firstnonvolatile nanotube switch and the second terminal of the secondnonvolatile nanotube switch can share a common node. The programmablenonvolatile nanotube select circuit can also include a field effecttransistor (FET) having a drain region, a source region, a channelregion positioned between the drain and source regions, and a gate nodein proximity to the channel region, wherein the gate node modulates theconductivity of the channel region and wherein the drain region of theFET is electrically coupled to the common node. The first plurality ofterminals can be electrically coupled to the first terminals of thenonvolatile nanotube switches and the second plurality of terminals canbe electrically coupled to the gate regions of the nonvolatile nanotubeswitches, and a plurality of transfer devices can be electricallycoupled to the common nodes of the programmable nonvolatile nanotubeselect circuits, the plurality of transfer devices can also beelectrically coupled to the third plurality of terminals so as toprovide routing between any two terminals of the third plurality ofterminals.

In one aspect, the present disclosure relates to a nanotubebi-directional buffer circuit that can include a first and secondbi-directional terminals, a first and second buffers, each buffer caninclude an input, an output, and a transfer device. The nanotubebi-directional buffer circuit can also include a programmablenonvolatile select circuit that can include a first two-terminalnonvolatile nanotube switch and a second two-terminal nonvolatilenanotube switch, wherein each of the first and second two-terminalnonvolatile nanotube switches that can include a first terminal and asecond terminal, wherein the first and second terminals of the firstnonvolatile nanotube switch are in contact with opposite ends of a firstnanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element, and the second terminal of the firstnonvolatile nanotube switch and the second terminal of the secondnonvolatile nanotube switch share a common node, and a field effecttransistor (FET) having a drain region, a source region, a channelregion positioned between the drain and source regions, and a gate nodein proximity to the channel region, wherein the gate node modulates theconductivity of the channel region and wherein the drain region of theFET is electrically coupled to the common node. The first bi-directionalterminal can be electrically coupled to the input of the first bufferand the output of the second buffer, wherein the second bi-directionalterminal can be electrically coupled to the input of the second bufferand the output of the first buffer, wherein the signal on the commonnode of the programmable nonvolatile nanotube select circuit can beelectrically coupled to the transfer device of the first buffer toenable signal flow from the second bi-directional terminal to the firstbi-directional terminal, wherein the complementary signal on the commonnode of the programmable nonvolatile nanotube select circuit can beelectrically coupled to the transfer device of the second buffer toenable signal flow from the first bi-directional terminal to the secondbi-directional terminal.

Other features and advantages of the disclosure invention will becomeapparent from the following description of the invention which isprovided below in relation to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an overview of field programmable devices (FPDs), sometimesreferred to as programmable logic devices (PLDs);

FIG. 2 is a block diagram of a programmable logic array (PLA);

FIG. 3 is a schematic of a programmable array logic (PAL™) device. PAL™is a trademark of AMD;

FIG. 4 is a block diagram of a complex programmable logic device;

FIG. 5 is a block diagram of a field programmable gate array (FPGA)including a plurality of configurable logic blocks (CLBs);

FIG. 6 is a block diagram of a configurable logic block (CLB) includinga look-up table (LUT), a D-flip flop, and a multiplexer;

FIG. 7 is a block diagram of a configurable logic block (CLB) includinga combinational logic function, a D-flip flop, and a multiplexer;

FIG. 8 is a block diagram of a field programmable gate array (FPGA)including an SRAM-configured programmable switch matrix;

FIG. 9 is a block diagram of a field programmable gate array (FPGA)including antifuse-based programmable wiring;

FIG. 10A illustrates a schematic of a nonvolatile nanotube switch (NV NTswitch);

FIGS. 10B and 10C show a nonvolatile nanotube switch (NV NT switch) inON and OFF states, respectively;

FIG. 10D shows a perspective drawing of a nonvolatile nanotube blockswitch;

FIG. 10E shows a perspective drawing of a cross point switch formedusing nonvolatile nanotube blocks described in FIG. 10D;

FIG. 10F shows a cross section of a nonvolatile nanotube block in serieswith steering (select) diodes shown in schematic form, with a firstdiode having a cathode in contact with a terminal of the nonvolatilenanotube block, or a second diode having an anode in contact with aterminal of the nonvolatile nanotube block;

FIG. 10G shows a perspective drawing of four memory cells (or four crosspoint switch cells) formed using the memory cell shown in FIG. 10F;

FIG. 11A shows a schematic representation of an NRAM™ cell;

FIG. 11B shows a schematic representation of a nonvolatile nanotubeselect circuit;

FIG. 12A shows the nonvolatile nanotube select circuit of FIG. 11B wiredas one cell in an X-Y array configuration;

FIG. 12B shows the nonvolatile nanotube select circuit shown of FIG. 12Aused to control the ON/OFF state of a transfer device;

FIG. 12C shows the nonvolatile nanotube select circuit of FIG. 12A usedas an input that controls a NAND logic circuit operation;

FIG. 12D shows the nonvolatile nanotube select circuit of FIG. 12A usedas an input that controls a NOR logic function operation;

FIG. 13 shows a nonvolatile nanotube field programmable gate array(NFPGA) with configurable logic blocks and programmable switch matricescontrolled by nonvolatile nanotube select circuits;

FIG. 14A shows a nonvolatile nanotube configurable logic block (NCLB)formed using transfer gates, NAND, NOR, and tristate circuits whoselogic function is determined by logic states provided nonvolatilenanotube select circuits;

FIG. 14B shows various logic circuit configurations formed by thenonvolatile nanotube configuration logic block of FIG. 14A based on thelogic state of nonvolatile nanotube select circuits that providenonvolatile configuration control states (or bits);

FIG. 15 shows various equivalent logic circuits corresponding to thevarious logic configurations formed by the nonvolatile nanotubeconfiguration logic block as shown in FIG. 14B;

FIG. 16 shows a nonvolatile nanotube programmable switch matrix withvarious signal routing configurations controlled by nonvolatile nanotubeselect circuits;

FIG. 17A shows a nonvolatile nanotube bidirectional buffer in which thedirection of signal flow is controlled by a nonvolatile nanotube selectcircuit;

FIG. 17B shows a nonvolatile nanotube enhanced bidirectional buffer inwhich the direction, polarity, and amplitude of signal flow iscontrolled by a nonvolatile nanotube select circuit;

FIG. 18 shows a nonvolatile nanotube programmable voltage generator thatgenerates a programmed on-chip voltage determined by a nonvolatilenanotube select circuit;

FIG. 19 shows a sixteen bit NRAM™ memory array;

FIG. 20 shows a nonvolatile nanotube configurable logic block with alook-up table formed using a 16 bit NRAM memory, a D-flip flop, and amultiplexer;

FIG. 21 shows a nonvolatile nanotube field programmable gate array(NFPGA) with configurable logic blocks and programmable switch matricescontrolled by nonvolatile NRAM™ memory outputs;

FIG. 22A shows a 1×6 nonvolatile NRAM™ memory architecture used as anNRAM™-based nonvolatile control bit generator that provides true andcomplement control bit outputs;

FIG. 22B shows a K×6 nonvolatile NRAM™ memory architecture used as anNRAM™-based nonvolatile control bit generator that provides true andcomplement control bit outputs;

FIG. 23 shows a nonvolatile nanotube configurable logic block (NCLB)formed using transfer gates, NAND, NOR, and tristate circuits whoselogic function is determined by nonvolatile true and complement controlbits generated by a nonvolatile NRAM™ memory such as described withrespect to FIG. 22A or FIG. 22B;

FIG. 24 shows a nonvolatile nanotube programmable switch matrix withvarious signal routing configurations controlled by nonvolatile true andcomplement control bits generated by a nonvolatile NRAM™ memory such asdescribed with respect to FIG. 22A or FIG. 22B;

FIG. 25 shows a nonvolatile nanotube static random access memory (NSRAM)cell formed by combining an SRAM cell and a pair of nonvolatile nanotubeswitching elements;

FIG. 26 shows another nonvolatile nanotube static random access memory(NSRAM) cell in which the pair of nonvolatile nanotube switchingelements used in FIG. 25 are replaced by a pair of NRAM™ cells with modecontrol transistors;

FIG. 27 shows two stages of a configuration control register thatprovides configuration control bits;

FIG. 28A shows two stages of a nonvolatile nanotube configurationcontrol register that provides nonvolatile configuration control bits.The logic state of the nanotube configuration control register (NCCR)may be stored in, and recalled from, nonvolatile high or low resistancestates in nonvolatile nanotube switches. Both nonvolatile nanotubeswitches (one per register stage) are shown in a low resistance (ON)state;

FIG. 28B shows the nonvolatile nanotube configuration control registerof FIG. 28A with both nonvolatile nanotube switches set in a highresistance (OFF) state;

FIG. 28C shows the nonvolatile nanotube configuration control registerof FIG. 28A with one nonvolatile nanotube switch is in a high resistance(OFF) state and another nonvolatile nanotube switch is in a lowresistance (ON) state;

FIG. 29 shows a nonvolatile nanotube configurable logic block (NCLB)formed using transfer gates, NAND, NOR, and tristate circuits whoselogic function is determined by nonvolatile true and complementconfiguration control bits provided by the nonvolatile nanotubeconfiguration control register shown in FIG. 28; and

FIG. 30 shows a nonvolatile nanotube programmable switch matrix withvarious signal routing configurations controlled by nonvolatile true andcomplement control bits provided by the nonvolatile nanotubeconfiguration control register shown in FIG. 28.

DETAILED DESCRIPTION

Integrated circuits for a wide variety of product applications in acompetitive environment require fast time-to-market for new designs andlow (or zero) non-recurring engineering cost (NRE) and low fabricationcost. As a result, the demand for field programmable devices (FPDs)solutions has increased rapidly. Low power is a requirement for mostapplications. Applications are increasingly portable so conservation ofbattery power is a requirement and nonvolatile operation isadvantageous, especially since integration levels (more function) areincreasing rapidly as is the requirement for high performance.

The present disclosure provides field programmable device (FPD) chipswith large logic capacity and field programmability that are in-circuitprogrammable (in-place in the package without requiring sockets). Theyuse small versatile nonvolatile nanotube switches that enable efficientarchitectures for dense low power and high performance chipimplementations and are compatible with low cost CMOS technologies andsimple to integrate (low additional mask count and few additionalprocess steps). Field programmable devices (FPDs) are also sometimesreferred to as programmable logic devices (PLDs) and the terms FPD andPLD are used interchangeably throughout the application.

User In-Circuit Programmable Switch Technologies

Overview of User Programmable Switch Technologies

Historically, CPLDs use EPROM and EEPROM switches and FPGAs use SRAM andantifuse switches. More recently, flash has also been used. As may beappreciated from the descriptions of FIGS. 8 and 9, the size,performance, and flexibility of switches used in FPGAs essentiallydetermines FPGA architecture because FPGAs use a large amount ofprogrammable wiring.

TABLE 1 Reprogrammable Typical Switch Type In Circuit Volatile VoltageTechnology EPROM NO NO Prog: 5-6 volts UV-CMOS (Out-of-Ckt: Operation:Std YES) EEPROM YES NO Prog: 10-15 V EE-CMOS Operation: higher voltageFLASH YES NO Prog: 10-15 V Flash-CMOS Operation: Std. SRAM YES YES Std.CMOS Antifuse NO NO Prog: 5-10 V. CMOS + (AF) Operation: Std. specialoxides & contacts NV NT YES NO Prog: 3-7 V. CMOS & Switch Operation:Std. patterned nanotube fabric

Table 1 is a summary of various switch types, their properties,programming and operating voltages, and underlying technologies. In somecases, more that one switch type may be used.

SRAMs used to control switches have the advantage of CMOS technologycompatibility with the latest CMOS technology generation andcompatibility with the standard (std.) technology operating voltagesbecause no programming is required. However, very large switch area andvolatile operation are disadvantages as well as high sensitivity toradiation and designs that can easily be copied. Antifuses have theadvantage of small area size but are not reprogrammable becauseantifuses are OTP so the chip architecture cannot be modified once it isprogrammed. Antifuses typically require 5-10 volts and relatively highcurrent in the 1-10 milliampere range. Antifuses have relatively highradiation tolerances and designs cannot easily be copied because“reverse engineering” is difficult. EPROMs with UV erase are typicallylimited to development prototypes. EEPROMs can be reprogrammedin-circuit but are larger than antifuses and require high programmingvoltage and require higher than standard operating voltages. Flash hashigh programming voltages but standard operating voltages. Flash devicesare small in size but larger than antifuses and may be more sensitive toradiation than antifuses.

Nonvolatile nanotube (NV NT) switches such as those described in U.S.patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled“Two-Terminal Nanotube Devices and Systems and Methods of Making,” U.S.Pat. No. 7,394,687 and U.S. patent application Ser. No. 12/165,007,filed on Jun. 30, 2008, entitled “Non-Volatile Shadow Latch Using aNanotube Switch,” U.S. patent application Ser. No. 11/835,583, filed onAug. 8, 2007, entitled “Latch Circuits and Operation Circuits HavingScalable Nonvolatile Nanotube Switches as Electronic Fuse ReplacementElements,” U.S. patent application Ser. No. 11/835,612, filed on Aug. 8,2007, entitled “Nonvolatile Resistive Memories Having ScalableTwo-Terminal Nanotube Switches,” U.S. patent application Ser. Nos.11/835,651, 11/835,759, 11/835,845, 11/835,852, 11/835,856, 11/835,865,each filed on Aug. 8, 2007, entitled “Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods of MakingSame,” and U.S. patent application Ser. No. 11/835,613, filed on Aug. 8,2007, entitled “Memory Elements and Cross Point Switches and Arrays ofSame Using Nonvolatile Nanotube Blocks,” may be used to form nonvolatilecross point switches that are as small as antifuses but can beprogrammed, erased, and reprogrammed multiple times. Such switches havea high tolerance to harsh environments such as high temperature and highradiation levels. NV NT switches may be combined with FETs to formnonvolatile NRAM™ memories with nonvolatile cells smaller than those ofSRAMs as described in U.S. patent application Ser. No. 11/274,967, filedon Nov. 15, 2005, entitled “Memory Arrays Using Nanotube Articles withReprogrammable Resistance.” NV NT switches may be combined with FETs toform NanoLogic™ circuits as described in U.S. patent application Ser.No. 11/835,583, filed on Aug. 8, 2007, entitled “Latch Circuits andOperation Circuits Having Scalable Nonvolatile Nanotube Switches asElectronic Fuse Replacement Elements,” U.S. patent application Ser. No.11/835,612, filed on Aug. 8, 2007, entitled “Nonvolatile ResistiveMemories Having Scalable Two-Terminal Nanotube Switches,” and U.S.Patent Application No. 61/039,204, filed on Mar. 25, 2008, entitled“Carbon Nanotube-Based Neural Networks and Methods of Making and UsingSame,” that may be used for configurable (programmable) logic functionsand programmable wire routing. So NV NT switches, which are compatiblewith CMOS technology and use programming voltages in the 3-7 volt rangeand corresponding programming currents in the tens of microamperes orless, are smaller than those of competing nonvolatile in-circuitreprogrammable technologies and operate at standard CMOS operatingvoltages and enable new more efficient CPLD and FPGA architectures. NVNT switch scaling of dimensions may be used to reduce programmingvoltages in future generations.

Nanotube switches fabricated as 2-D NV NT switches with a horizontalorientation or as 3-D NV NT block switches with a vertical orientationare illustrated in FIGS. 10A-10D and described in the above referencedpatents. Other types of hybrid NanoLogic™ circuits may be fabricated asshown in U.S. Pat. Nos. 7,115,901 and 7,268,044 and U.S. patentapplication Ser. No. 11/731,946, each entitled “Non-VolatileElectromechanical Field Effect Devices and Circuits Using Same andMethods of Forming Same,” U.S. Pat. No. 6,982,903, entitled “FieldEffect Devices Having a Source Controlled via a Nanotube SwitchingElement,” U.S. Pat. No. 7,280,394, entitled “Field Effect Devices Havinga Drain Controlled via a Nanotube Switching Element,” U.S. Pat. No.7,211,854 and U.S. patent application Ser. No. 11/742,290, filed on Apr.30, 2007, each entitled “Field Effect Devices Having a Gate Controlledvia a Nanotube Switching Element,” U.S. Pat. No. 7,301,802, entitled“Circuit Arrays Having Cells with Combinations of Transistors andNanotube Switching Elements,” and U.S. Pat. No. 7,112,493 and U.S.patent application Ser. No. 11/527,127, filed on Sep. 26, 2006, eachentitled “Method of Making Non-Volatile Field Effect Devices and Arraysof Same.” Also, NanoLogic™ circuits that use only nanotube elements arealso possible. Such nanotube-only type of NanoLogic™ circuits aredescribed in U.S. Pat. No. 7,115,960 and U.S. patent application Ser.No. 11/542,524, filed on Oct. 3, 2006, each entitled “Nanotube-BasedSwitching Elements,” U.S. Pat. Nos. 6,990,009, 7,339,401 and U.S. patentapplication Ser. No. 11/971,476, filed on Jan. 9, 2008, each entitled“Nanotube-Based Switching Elements with Multiple Controls,” U.S. Pat.No. 7,228,970 and U.S. patent application Ser. No. 11/929,076, filed onOct. 30, 2007, each entitled “Integrated Nanotube and Field EffectSwitching Device,” U.S. Pat. No. 7,329,931 and U.S. patent applicationSer. No. 12/029,118, filed on Feb. 11, 2008, each entitled “ReceiverCircuit Using Nanotube-Based Switches and Transistors,” U.S. Pat. No.7,330,709 and U.S. patent application Ser. No. 12/029,661, filed on Feb.12, 2008, each entitled “Receiver Circuit Using Nanotube-Based Switchesand Logic,” U.S. Pat. Nos. 7,164,744, 7,265,575 and U.S. patentapplication Ser. No. 11/897,812, filed on Aug. 31, 2007, each entitled“Nanotube-Based Logic Driver Circuits,” U.S. Pat. Nos. 7,161,403,7,405,605 and U.S. patent application Ser. No. 12/147,315, each entitled“Storage Elements Using Nanotube Switching Elements,” and U.S. Pat. Nos.7,167,026, 7,288,961 and U.S. patent application Ser. No. 11/928,538,filed on Oct. 30, 2007, each entitled “Tri-state Circuit Using NanotubeSwitching Elements,” and may be volatile or nonvolatile in operation.This specification will focus on NV NT switches and NV NT blocks fornonvolatile multiple-cycle cross point switches, hybrid FET-nanotubecombinations for NRAM™ storage elements, and NanoLogic™ circuits.

User In-Circuit Nonvolatile Programmable Switch Technologies UsingNanotube Switches, Nanotube Cross Point Switches, NRAM™ Memories, andNanoLogic™ Circuits

Examples of certain embodiments of nonvolatile nanotube-baseduser-programmable switches for use in nanotube FPGA (NFPGA) Logic,nanotube SPLD (NSPLD) logic, and nanotube CPLD (NCPLD) logic aredescribed further below in FIGS. 10A-10G and 11, 12. These includetwo-dimensional and three-dimensional nonvolatile nanotube switches anddense multi-cycle bidirectional cross point switches, dense directionalcross point switches, nonvolatile NRAM™ memory cells, and nonvolatileNanoLogic™ circuits.

Nonvolatile nanotube (NV NT) switch 1000 illustrated in FIG. 10A is aschematic illustration of a two terminal switch with terminals T1 and T2in contact with opposite ends of a patterned nanofabric (patternednon-woven nanotube fabric) as illustrated in U.S. Pat. Nos. 6,706,402,6,942,921 and U.S. patent application Ser. Nos. 10/774,682, filed onFeb. 9, 2004, 11/111,582, filed on Apr. 21, 2005, each entitled“Nanotube Films and Articles,” U.S. Pat. Nos. 6,835,591, 7,264,990, and7,335,528, each entitled “Methods of Nanotube Films and Articles,” andU.S. patent application Ser. No. 10/341,130, filed on Jan. 13, 2003,entitled “Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements andArticles.” NV NT switch 1000 may be viewed as a resistor that changesresistance value, increasing or decreasing resistance, as a function ofapplied currents and voltages as described in U.S. patent applicationSer. No. 11/280,786, filed on Nov. 15, 2005, entitled “Two-TerminalNanotube Devices and Systems and Methods of Making,” and U.S. patentapplication Ser. No. 11/835,583, filed on Aug. 8, 2007, entitled “LatchCircuits and Operation Circuits Having Scalable Nonvolatile NanotubeSwitches as Electronic Fuse Replacement Elements,” U.S. patentapplication Ser. No. 11/835,612, filed on Aug. 8, 2007, entitled“Nonvolatile Resistive Memories Having Scalable Two-Terminal NanotubeSwitches.” Resistance values are nonvolatile and are retained(remembered) even if power is removed (switched OFF). In applicationssuch as NRAM™ storage cells, switches may be switched between ON and OFFstates in which the ON state resistance may be in the 10 k Ohm to 1M Ohmrange and the OFF state is typically 1 G Ohm and higher.

It is also possible to store multiple bits on a single NV NT switch 1000using multiple ON resistance values and one OFF value for increasedmemory density. For example, four resistance states store two bits ofinformation on the same switch as described in U.S. patent applicationSer. No. 11/835,583, filed on Aug. 8, 2007, entitled “Latch Circuits andOperation Circuits Having Scalable Nonvolatile Nanotube Switches asElectronic Fuse Replacement Elements,” U.S. patent application Ser. No.11/835,612, filed on Aug. 8, 2007, entitled “Nonvolatile ResistiveMemories Having Scalable Two-Terminal Nanotube Switches.”Multi-resistance (greater than two) values may also be used in analogapplications as described in U.S. patent application Ser. No.11/835,583, filed on Aug. 8, 2007, entitled “Latch Circuits andOperation Circuits Having Scalable Nonvolatile Nanotube Switches asElectronic Fuse Replacement Elements,” U.S. patent application Ser. No.11/835,612, filed on Aug. 8, 2007, entitled “Nonvolatile ResistiveMemories Having Scalable Two-Terminal Nanotube Switches.” In thoseapplications featuring multi-resistance (greater than two) values, NV NT1000 switches may be referred to as NANRISTORs. Since most of the NV NT1000 switches as used in this application are digital (ON or OFF) theterm NV NT switch is used.

Switch resistance values for NV NT NRAM™ cells and NanoLogic™ circuitstypically range in ON values between 10 k Ohm and 1M Ohm. OFF resistancevalues are typically 1 G Ohm or higher. In the case of cross pointswitches, ON resistance values may be in the range of 50 Ohms to 500Ohms for example because of time delay (performance) considerations.Resistance values are determined by material and geometric properties(dimensions) such as channel length and width and the density of thenanotube fabric. As illustrated above, different applications usedifferent values of NV NT switch resistance values.

FIG. 10B shows a planar voltage contrast SEM image of a two terminal NVNT switch 1010 in an ON state in which nanotube channel region 1012forms a continuous path between terminals T1 and T2. FIG. 10C shows twoterminal NV NT switch 1010′ in an OFF state. The same physical NV NTswitch is used for both FIGS. 10B and 10C. However, NV NT switch 1010′is in an OFF state; that is there no continuous path between terminalsT1 and T2. The nanotube channel region in FIG. 10C is electricallydiscontinuous with a portion of nanotube channel region 1018A in an OFFstate and another series portion of nanotube channel regions 1018B in anON state. FIGS. 10B and 10C are described in greater detail in U.S.patent application Ser. Nos. 11/835,651, 11/835,759, 11/835,845,11/835,852, 11/835,856, 11/835,865, each filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same.”

Programmable Wiring Using Nonvolatile Nanotube Cross Point Switches

In cross point switch applications which require high density,vertically oriented nonvolatile nanotube (NV NT) blocks may be used asillustrated by a perspective view of NV NT block 1020 in FIG. 10D. NV NTblock 1020 is formed by etching a relatively thick (30 to 40 nm forexample) nanofabric layer to form nanofabric block 1022 with bottomcontact 1023 and top contact 1024. NV NT block 1020 switches may bein-circuit programmed between ON and OFF states multiple times. So forexample, programmable antifuse 940 shown in FIG. 9 (which cannot beprogrammed or configured in-circuit) may be replaced with in-circuitprogrammable NV NT block 1020 at comparable densities.

FIG. 10E shows a perspective drawing of bidirectional cross point switcharray 1025 formed using four NV NT blocks 1030-1, 1030-2, 1030-3, and1030-4 corresponding to NV NT block 1020 in FIG. 10D. Traces 1032-1 and1032-2 correspond to vertical wires 920 and traces 1034-1 and 1034-2correspond to horizontal wires 930 in FPGA 900 schematic drawingillustrated in FIG. 9. These orthogonal pairs of traces in contact withbottom and top surfaces of NV NT blocks provide FPGA wiring and contactsto the four NV NT blocks thereby forming bidirectional cross pointswitch array 1025 that supports in-circuit programming (routing). Trace1032-1 forms array wiring and the bottom contact of NV NT blocks 1030-1and 1030-3 and trace 1032-2 forms array wiring and the bottom contact ofNV NT blocks 1030-2 and 1030-4. Trace 1034-1 forms array wiring and thetop contact of NV NT blocks 1030-1 and 1030-2 and trace 1034-2 formsarray wiring and the top contact of NV NT blocks 1030-3 and 1030-4.

Bidirectional cross point switch array 1025 illustrated in perspectiveview in FIG. 10E enables or prevent bidirectional flow of signals,currents, voltages, or power in a densely packed array of NV NT blocknonvolatile in-circuit programmable switch matrix. It may be desirablefor some dense switch matrices to enable or prevent unidirectional flowof signals, currents, voltages, or power in dense arrays nonvolatileswitches. FIG. 10F illustrates a nonvolatile nanotube (NV NT) diode 1035that includes a NV NT block 1038 corresponding to NV NT block 1020 inseries with a diode and is described in further detail in U.S. patentapplication Ser. Nos. 11/835,651, 11/835,759, 11/835,845, 11/835,852,11/835,856, 11/835,865, each filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same.” NV NT block 1038 conductscurrent in any direction and is not sensitive to voltage polarity. NV NTblock 1038 includes NV NT block 1040, bottom contact 1042, and topcontact 1044. Diode 1046 illustrated schematically is oriented such thatthe cathode is connected to bottom contact 1042 and the anode isconnected to contact 1050 enabling vertical current flow in the upwarddirection. Alternatively, diode 1048 illustrated schematically isoriented such that the anode is connected to bottom contact 1042 and thecathode is connected to contact 1050 enabling vertical current flow inthe downward direction. Diodes 1046 and 1048 may be may be Schottkydiodes, PN diodes, or diodes formed with nanotube fabric anodes asdescribed in U.S. patent application Ser. Nos. 11/835,651, 11/835,759,11/835,845, 11/835,852, 11/835,856, 11/835,865, each filed on Aug. 8,2007, entitled “Nonvolatile Nanotube Diodes and Nonvolatile NanotubeBlocks and Systems Using Same and Methods of Making Same.”

Unidirectional cross point switch array 1060 illustrated in perspectiveview in FIG. 10G enables or prevent unidirectional flow of signals,currents, voltages, or power in a densely packed array of NV NT blocknonvolatile in-circuit programmable switch matrix. Unidirectional crosspoint switch array 1060 formed using four nonvolatile nanotube (NV NT)diodes 1065-1, 1065-2, 1065-3, and 1065-4 that correspond to NV NT diode1035 illustrated in FIG. 10F and illustrates a Schottky diode version ofdiode 1046 as the current steering device. The NV NT diode 1065-1structure is representative of NV NT diodes 1065-2, 1065-3, and 1065-4.NV NT diode 1065-1 is formed by NV NT block 1075-1 and Schottky diode1070-1. Note that PN diode and diodes with nanotube anodes may also beused as described in U.S. patent application Ser. Nos. 11/835,651,11/835,759, 11/835,845, 11/835,852, 11/835,856, 11/835,865, each filedon Aug. 8, 2007, entitled “Nonvolatile Nanotube Diodes and NonvolatileNanotube Blocks and Systems Using Same and Methods of Making Same.”Schottky diode 1070-1 is formed by anode 1071-1 in contact with N− poly1072-1, in contact with N+ poly 1073-1; NV NT block 1075-1 is formed byNT cube 1077-1 in contact with bottom contact 1076-1 and top contact1078-1. Traces 1080-1 and 1080-2 correspond to vertical wires 920 andtraces 1082-1 and 1082-2 correspond to horizontal wires 930 in FPGA 900schematic drawing illustrated in FIG. 9. These orthogonal pairs oftraces in contact with diode 1070-1 anode 1071-1 for example and topcontact 1078-1 for example of NV NT diode 1065-1 and corresponding diodeanodes and top contacts of NV NT diodes 1065-2, 1065-3, and 1065-4simultaneously provide unidirectional FPGA wiring and four NV NT diodesthereby form unidirectional cross point switch array 1060 that supportsin-circuit programming. Trace 1080-1 forms array wiring and the contactto anodes of corresponding NV NT diodes 1065-1 and 1065-3 and trace1080-2 forms array wiring and the top contact of NV NT diodes 1065-2 and1065-4. Trace 1082-1 forms array wiring and the top contact of NV NTdiodes 1065-1 and 1065-2 and trace 1082-2 forms array wiring and the topcontact of NV NT diodes 1065-3 and 1034-4.

High Application Function Security Using Programmable Wiring withNonvolatile Nanotube Cross Point Switches and Programmable Logic Blocks

There are certain sensitive applications in which it is desirable that alogic application function remain proprietary. Such applications includeintelligence functions, military applications, industrial secrets, andothers. However, there are situations in which a logic applicationfunction can be determined based on hardware implementations such as inintegrated circuit chips for example in which such chips may be stolenor fall into unfriendly territory. In cases where hard wire connectionsare permanent, hard wires can be traced and the logic function can beidentified. Alternatively, in some cases, chips may be interrogatedelectronically by a security breach in an internet connection. What isneeded are effective countermeasures that provide high applicationfunction security.

A logic application function can be identified based on the logic blocksused and wiring interconnections between the logic blocks. A logicapplication function may be secured by reprogramming one or moreprogrammable wiring interconnections between individual wires and logic(or logic and memory) blocks if a security event (breach) is detected.In another approach, a logic application function may be secured byreprogramming one or more programmable logic blocks if a security eventis detected. In still another approach, a logic application function maybe secured by both reprogramming one or more programmable wiringinterconnections and further reprogramming one or more programmablelogic blocks if a security event is detected. These and other similarelectronic countermeasure approaches to logic application functionsecurity require dense nonvolatile switches that can be programmedmultiple times and changed in case of a security event.

In certain situations, a security event may be detected and sufficienttime exists to deploy electronic countermeasures such as thereprogramming of integrated circuit chips. If a security event isdetected, the logic application functions may be changed by alteringprogrammable wiring connections, altering programmable logic blocks, oraltering both wiring connections and logic blocks as described furtherabove. However, this requires dense nonvolatile switches such asnonvolatile nanotube cross point switches (FIGS. 10D, 10E, 10F, and 10G)and other nonvolatile nanotube switch types such as the NV NT switchillustrated in FIGS. 10A-10C that can be programmed multiple times.One-time-programmable (OTP) antifuses, or any kind of OTP switch, cannotbe used because OTP switches cannot be reprogrammed. Additional examplesof nonvolatile nanotube-based switches are illustrated further belowwith respect to FIGS. 11 and 12 for example, and various FPGA logicexamples also illustrated further below. In case of a security event,logic application functions may be altered in many ways, such as, butnot limited to, reprogramming said logic application functions in arandom manner or setting a plurality of programmable interconnections toan open state. Alternatively, the logic application function may bealtered such that a different logic application function is formed todeliberately mislead.

In other situations, a security event may take place which is undetectedor in which there is insufficient time to deploy electroniccountermeasures. For example, an integrated circuit chip that includeshigh application function security logic may be stolen. In thissituation, chip designs that make the application of advanced reverseengineering (failure analysis) techniques difficult may be used toprotect high application function security chips. For example, a highapplication security function may include extra circuits, devices, andinterconnections for the purpose of complicating reverse engineering ofintegrated circuit chips. For hard-wired logic functions,interconnections and contact regions may be traced (that is,interconnections between circuit elements detected using electronicequipment such as scanning electron microscopes) at high magnificationto identify logic functions. If antifuses are used instead of contacts,it is difficult to tell whether an antifuse has been activated (isconductive) and forms a contact or if the antifuse is nonactivated(nonconducting) by examining the chip regions under high magnification.However, since cross sectional techniques to determine oxide integrityare well known in the industry, the logic function may be reverseengineered using known failure analysis techniques to see if an antifuseoxide has been ruptured and is in a conductive state or if the oxide isintact and the antifuse is in a noncontactive state.

Cross point switches using patterned nanofabric, as described in U.S.patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled“Two-Terminal Nanotube Devices and Systems and Methods of Making,” toform nonvolatile nanotube switches such as illustrated in FIGS. 10D and10E are nearly impossible to reverse engineer. Typically, the patternednanofabric cross point switch area (or volume) is about 90% void orfilled with non-carbon nanotube material. Cross sectioning such a crosspoint switch tends to destroy it completely. Even if the switch is notdestroyed completely, it is likely to be damaged so that the state ofthe switch (low or high resistance) cannot be reliably determined.

Another approach to nanotube-based security is to leverage thedifficulty of reverse engineering cross point switches using patternednanofabric (as described further above) and to include patternednanofabric contacts in logic as part of logic wiring (interconnects)that are very difficult to reverse engineer. This is possible becausesuch patterned nanofabric contacts are (or can be made) normally asconducting nonvolatile nanotube crosspoint switches as-fabricated.Keeping the logic operating voltages below the switching voltage of thenonvolatile nanotube cross point switches enables the patternednanofabric to act as a patterned nonfabric contact. The switchingvoltage of nonvolatile nanotube cross point switches may be increased towell above that the logic voltage swings as needed as to ensure thatpatterned nanofabric contacts remain conductive, as described in U.S.Pat. Nos. 6,706,402, 6,942,921 and U.S. patent application Ser. Nos.10/774,682, filed on Feb. 9, 2004, 11/111,582, filed on Apr. 21, 2005,each entitled “Nanotube Films and Articles.”

NRAM™ Cells and NanoLogic™ Analog and Digital Circuits

FIG. 11A illustrates NRAM™ cell 1100 comprising NV NT switch 1110 andFET 1120 in series. Nonvolatile NRAM™ memories are formed with multipleNRAM cells similar to NRAM cell 1100 as described in U.S. patentapplication Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled“Two-Terminal Nanotube Devices and Systems and Methods of Making,” andU.S. patent application Ser. No. 11/274,967, filed on Nov. 15, 2005,entitled “Memory Arrays Using Nanotube Articles with ReprogrammableResistance,” and with respect to FIG. 19 further below, with nonvolatilecells smaller in area than volatile 6 FET SRAM cells. Multiple wordlines (not shown) are arranged horizontally and in contact with gates ofFETs corresponding to gate G of FET 1120; bit lines (not shown)essentially orthogonal to word lines are arranged vertically and contacta diffusion terminal corresponding to terminal T1 in FIG. 11A. One sideof the NV NT switches corresponding to NV NT switch 1110 is in contactwith a terminal of FETs such as FET 1120 and the other side is incontact with common reference lines (not shown) in contact with aterminal of NV NT switches such as NV NT switch 1110. Such contacts maybe formed with reference lines that may be parallel to word or bitlines, or may be formed by a reference plane (not shown), with referencevoltage held at a reference voltage such as ground.

In operation, NRAM™ cell 1100 may be programmed to a high resistancestate such as 1 G Ohm or higher for example, and a low resistance statein the 100 k Ohm to 1M Ohm range for example. Voltages in the range of3-7 volts are applied for write 1 (program) and write 0 (erase)operations with readout voltages in the 1.5 to 2.5 volt range. Operatingconditions are a function of the NV NT switch material and geometricalcharacteristics such as distance between terminal contacts to thepatterned nanofabric material. Waveform examples are illustrated in U.S.patent application Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled“Two-Terminal Nanotube Devices and Systems and Methods of Making,” U.S.patent application Ser. No. 11/274,967, filed on Nov. 15, 2005, entitled“Memory Arrays Using Nanotube Articles with Reprogrammable Resistance,”U.S. patent application Ser. No. 11/835,583, filed on Aug. 8, 2007,entitled “Latch Circuits and Operation Circuits Having ScalableNonvolatile Nanotube Switches as Electronic Fuse Replacement Elements,”U.S. patent application Ser. No. 11/835,612, filed on Aug. 8, 2007,entitled “Nonvolatile Resistive Memories Having Scalable Two-TerminalNanotube Switches.”

In order to further facilitate in-circuit configurable (programmable)logic blocks (cells, functions) and in-circuit programmable switchmatrices for routing signals, currents, voltages, and/or power forexample, NanoLogic™ circuits with various combinations of nonvolatileswitches and FETs may be formed. NanoLogic™ circuits may be used inFPGAs, SPLDs, CPLDs, and in other digital circuit applications as wellas analog applications. FPGA, SPLD, and CPLD programmable logicfunctions configured using nanotube-based NanoLogic™ and memoryfunctions such as NRAM™ may be referred to as NFPGA, NSPLD, and NCPLDlogic functions, respectively.

FIG. 11B illustrates an embodiment of NanoLogic™ configurable(programmable) NV NT select circuit 1150 formed using NV NT switch 1155(SW1) and NV NT switch 1160 (SW2) sharing a common node referred to asselect node 1170. Terminals T1 and T2 are connected to a second terminalof NV NT switches 1155 and 1160, respectively. FET 1165 has a diffusionconnected to common select node 1170 and the other diffusion connectedto a reference such as ground as described in U.S. Patent ApplicationNo. 61/039,204, filed on Mar. 25, 2008, entitled “Carbon Nanotube-BasedNeural Networks and Methods of Making and Using Same.”

In operation, when a logic function is programmed, FET 1165 is activated(ON) during program (write 1) or erase (write 0) operations by applyinga high voltage to gate G of FET 1165 which connects select node 1170 toground and provides a current path between terminal T1 and ground andterminal T2 and ground through NV NT switches 1155 and 1160,respectively. Combinations of erase and program operations are used toset resistance states (values) of NV NT switches 1155 and 1160. Eraseand program operations are described further above with respect to FIG.11A and in more detail in U.S. patent application Ser. No. 11/280,786,filed on Nov. 15, 2005, entitled “Two-Terminal Nanotube Devices andSystems and Methods of Making,” U.S. patent application Ser. No.11/274,967, filed on Nov. 15, 2005, entitled “Memory Arrays UsingNanotube Articles with Reprogrammable Resistance,” U.S. patentapplication Ser. No. 11/835,583, filed on Aug. 8, 2007, entitled “LatchCircuits and Operation Circuits Having Scalable Nonvolatile NanotubeSwitches as Electronic Fuse Replacement Elements,” U.S. patentapplication Ser. No. 11/835,612, filed on Aug. 8, 2007, entitled“Nonvolatile Resistive Memories Having Scalable Two-Terminal NanotubeSwitches.” NV NT switches 1155 and 1160 may be viewed as NANRISTORS.These resistance states (values) remain nonvolatile even after power isremoved or lost. After program or erase operations, FET 1165 is in an(OFF) state by applying a low voltage such as ground to gate G of FET1165 and select node 1170 is disconnected from ground. NV NT selectcircuit 1150 is now ready to provide a configured (programmed) logicblock function operating at 2.5 volts for example. Note that whileNanoLogic™ circuits are designed to be in-circuit programmed, this doesnot preclude programming in sockets for example as is done in some oldertechnologies. In fact, NanoLogic™ circuits may be embedded and operatein chips with older programmable technologies and with CMOS digital andanalog circuits. Note that the terms configurable and programmable areused interchangeably.

During logic operation, after the configurable logic function has beenprogrammed and is stored in a nonvolatile state by NV NT switches 1155and 1160 operating voltages are kept sufficiently low, less than 3 voltsfor example, so that the resistance states (values) of NV NT switches1155 and 1160 are not changed (disturbed) under NFPGA, NCPLD, NSPLD, andother programmable logic function operation. If NV NT switch 1155 is inhigh resistance state, 1 G Ohm for example, and NV NT switch 1160 is inlow resistance state, 100 k Ohms for example, and if T1 is at an on-chipvoltage of V_(DD)=2.5 volts and T2 is at a reference voltage such asground (zero volts), then select node 1170 voltage will be atapproximately 0 volts. However, if switch NV NT switch 1155 is in a lowresistance state, 100 k Ohm for example, and NV NT switch 1160 is in ahigh resistance state, 1 G Ohm for example, then select node 1170voltage will be at 2.5 volts. FET 1165 is OFF during logic operations.

Logic operation has been described in terms of applying inputs toterminals T1 and T2 to generate a select node 1170 output voltage.However, an input voltage may be applied to select node 1170 and outputvoltages may be generated at terminals T1 and T2 based on the resistancestates (values) of NV NT switches 1155 and 1160 and circuits (not shown)connected to terminals T1 and T2.

FIGS. 12A-12D illustrate various embodiments of NanoLogic™ nonvolatilenanotube configurable logic blocks (circuits, functions, cells) withinputs X1 and X2 to NV NT switches and a mode control input Y connectedto the gate of a mode control (program/erase or operate) FET. Inputs X1and X2 and mode control input Y may be shared by multiple NanoLogic™circuits as illustrated further below in FIG. 13. The NanoLogic™circuits illustrated in FIG. 12 correspond to combinatorial logicfunction 710 illustrated in FIG. 7. Flip flops and multiplexers oftenincluded as part of configurable logic blocks, as illustrated in FIG. 7,are not shown in FIG. 12 but may be included as needed.

NanoLogic™ programmable NV NT select circuit 1200 illustrated in FIG.12A corresponds to programmable NV NT select circuit 1150 illustrated inFIG. 11B. Inputs X1 and X2 correspond to inputs T1 and T2, respectively;switches 1205 and 1210 correspond to switches 1155 and 1160,respectively; FET 1215 corresponds to FET 1165. Mode control input Y isconnected to the gate of FET 1215 which corresponds to gate G of FET1165. Select node 1220 corresponds to select node 1170. Programmable NVNT select circuit 1200 operation corresponds to the operation ofprogrammable NV NT select circuit 1150 described further above withrespect to FIG. 11B.

FIG. 12B illustrates programmable NanoLogic™ circuit 1240 in whichprogrammable NV NT select circuit 1200-1 with select node 1225-1corresponds to programmable NV NT select circuit 1200, and controls thegate voltage of FET 1230 transfer device. The logic function ofprogrammable NV NT select circuit 1200-1 is determined as describedfurther above with respect to programmable NV NT select circuits 1200and 1150 and retains the programmed logic function even if power isremoved or is lost.

In operation, select node 1225-1 turns FET 12300N if it is at a highvoltage such as 2.5 volts and turns FET 1230 OFF if is at a low voltagesuch as ground. When FET 1230 is ON, signal flow, voltage distribution,current distribution, and power distribution are enabled; and when FET1230 is in an OFF state, then transmission of these functions isdisabled. NanoLogic™ circuit 1240 may be used to control switches thatroute signals as illustrated further below with respect to FIGS. 13, 16,17A, and 17B. Also, multiple NanoLogic™ circuits 1240 may be combined togenerate larger nonvolatile nanotube logic blocks (circuits, functions,cells) as illustrated in FIG. 14, and corresponding FIG. 15 and FIG.14B.

FIG. 12C illustrates programmable NanoLogic™ circuit 1250 in whichprogrammable NV NT select circuit 1200-2 with select node 1225-2corresponds to programmable NV NT select circuit 1200, and controls aninput voltage of NAND gate 1260. The logic function of programmable NVNT select circuit 1200-2 is determined as described further above withrespect to programmable NV NT select circuits 1200 and 1150 and retainsthe programmed logic function even if power is removed or is lost.

In operation, if select node 1225-2 is at a high voltage state H such as2.5 volts then NAND gate 1260 operates as a two input NAND gate withinputs A and B and the complement of A·B (A·B)_(C) as the output asillustrated in table 1265. However, when select node 1225-2 is at a lowvoltage state L such as zero volts, NAND gate 1260 output remains at ahigh voltage state H such as 2.5 volts independent of inputs A and B asillustrated in table 1265. Programmable NanoLogic™ circuit 1250 may beused as a NV NT configurable (programmable) logic block as illustratedin FIG. 13.

FIG. 12D illustrates programmable NanoLogic™ circuit 1270 in whichprogrammable NV NT select circuit 1200-3 with select node 1225-3corresponds to programmable NV NT select circuit 1200, and controls aninput voltage of NOR gate 1280. The logic function of programmable NV NTselect circuit 1200-3 is determined as described further above withrespect to programmable NV NT select circuits 1200 and 1150 and retainsthe programmed logic function even if power is removed or is lost.

In operation, if select node 1225-3 is at a low voltage state L such aszero volts then NOR gate 1280 operates as a two input NOR gate withinputs A and B and the complement of the sum of A plus B (A+B)_(C) asthe output as illustrated in table 1275. However, when select node1225-3 is at a high voltage such as 2.5 volts, NOR gate 1280 outputremains at a low voltage state L such as zero volts independent ofinputs A and B as illustrated in table 1275. Programmable NanoLogic™circuit 1270 may be used in a NV NT configurable (programmable) logicblock as illustrated in FIG. 13.

Nanotube Nonvolatile NFPGA Logic

FPGA architectures are dominated by interconnects. FPGAs are thereforemuch more flexible in terms of the range of designs that can beimplemented and logic functions in the hundreds of thousands to millionsand tens-of-millions of equivalent logic gates may be realized. Inaddition, the added flexibility enables inclusion of higher-levelembedded function such adders, multipliers, CPUs, and memory. The addedinterconnect (routing) flexibility of FPGAs also enables partialreconfiguration such that one portion of an FPGA chip may bereprogrammed while other portions are running FPGAs that can bereprogrammed while running may enable reconfigurable computing(reconfigurable systems) that reconfigure chip architecture to betterimplement logic tasks.

Nonvolatile nanotube switches combined with basic building blocks ofFPGAs such as configurable logic blocks (CLBs), programmable switchmatrices (PSMs), bidirectional buffers (BiDi buffers) result denser, lowpower, and high performance nonvolatile nanotube building blocks such asNCLBs, NPSMs, N-BiDi buffers, and other functions that enablenonvolatile nanotube FPGA (NFPGA) logic operation.

Nonvolatile nanotube select circuits (NV NT select circuits) describedin U.S. Patent Application No. 61/039,204, filed on Mar. 25, 2008,entitled “Carbon Nanotube-Based Neural Networks and Methods of Makingand Using Same,” are combined with CLB and PSM functions to form NCLBand NPSM building blocks that may be integrated to form NFPGA logic asdescribed with respect to FIGS. 13-18 illustrated further below.

NFPGAs which include NCLB, NPSM, N-BiDi, nonvolatile nanotubeprogrammable voltage generators and other logic and memory functions mayreprogrammed in case of a security event to protect high applicationfunction security integrity as described further above. Thus, forexample, configuration control bits supplied by NV NT select circuits orother NanoLogic™ circuits, NRAM™ memory arrays, or nonvolatilenanotube-based shift registers can be dynamically reprogrammed therebyaltering the NFPGA logic function in response to a security event(threat).

Nanotube Configurable Logic Blocks (NCLB) & Nanotube Programmable SwitchMatrix (NPSM) Using Nonvolatile Nanotube Select Circuits

NFPGA Function and Operation Using Nonvolatile Nanotube Select Circuits

FIG. 13 illustrates a block diagram of an embodiment of NFPGA 1300formed using NanoLogic™ circuits that include nonvolatile nanotube (NVNT) select circuits (labeled NT SEL1-5) as part of nanotube configurablelogic blocks (NCLBs) such as NCLB 1320 for example and nanotubeprogrammable switch matrices (NPSMs) such as NPSM 1340-1. NFPGA 1300also includes nanotube bidirectional buffers such as NT BiDi buffer 1375that controls the direction of signal flow in global wire 1380. Flipflops and multiplexers (shown in FIG. 7) may be included as well.Multiple NV NT select circuits share select/program/operate row lines X1. . . X8 and mode control lines Y1 . . . Y3.

The NFPGA 1300 logic function is configured by performing program orerase operations on NV NT select circuits, labeled NT SEL1-5 in FIG. 13,using rows of select/program/operate lines X1 . . . X8 and columns ofmode control lines Y1 . . . Y3 as described further above with respectto NV NT select circuits 1150 and 1200. Multiple nanotube configurablelogic blocks (NCLBs), nanotube programmable switch matrices (NPSMs), andNT BiDi Buffers such as NT BiDi Buffer 1375 are configured (programmed)and define the NFPGA 1300 logic function. Then, X1 . . . X8 voltages areset to a combination of high and low voltage values and Y1 . . . Y3 areset to a low voltage such as ground to enable NFPGA 1300 logic operationas described further above with respect to NV NT select circuit 1150 inFIG. 11B.

NCLB 1320 corresponds to NanoLogic™ circuit 1250 illustrated in FIG. 12Cand flip flops and multiplexers (not shown) as needed such asillustrated in FIG. 7; NPSM 1340-1 corresponds to NanoLogic™ circuit1240 illustrated in FIG. 12B; NPSM 1340-2 also corresponds to NanoLogic™circuit 1240; NCLB 1360 corresponds to NanoLogic™ circuit 1270illustrated in FIG. 12D and flip flop and multiplexers (not shown) asneeded such as illustrated in FIG. 7; NCLB 1350 includes NT SEL4 alsoreferred to as NV NT select circuit 1357 that corresponds to NV NTselect circuit 1200 which controls the operation of multiplexer 1355 andmay include flip flops and other multiplexers (not shown) as illustratedin FIG. 7. CLB functions such as 1305 and 1370 may include configurablelogic functions such as illustrated in FIGS. 6 and 7 and may or may notinclude NanoLogic™ functions. Wiring region 1310 shows horizontal wiresthat may be used for various interconnections (not shown). NT BiDiBuffer 1375 controls the direction of signal flow on wire 1380 asexplained further below with respect to FIG. 17.

In logic configuration operations, NV SEL1 . . . NV SEL5 share controland mode select lines X1 . . . X8 and Y1 . . . Y3, respectively. Inperforming erase and programming operations, it is important not todisturb other NV NT select circuits sharing the same control and modeselect lines. One method of implementing a configuration-settingoperation is to first erase all pairs of NV NT switches to a highresistance (OFF) state such illustrated by NV NT switch 1010′ in FIG.10C which corresponds to NV NT switches 1155 and 1160 illustrated inFIG. 11B and NV NT switches corresponding to NV NT switches 1205 and1210 illustrated in FIG. 12A, along pairs of row lines such as X1 andX2. Then, program selected individual NV NT switches to a low resistance(programmed) state, leaving unselected NV NT switches in a highresistance (erased) state as described further below. Another method ofimplementing a configuration-setting operation is to first program allpairs of NV NT switches to a low resistance (ON) state such asillustrated by NV NT switch 1010 in FIG. 10B which corresponds to NV NTswitches 1155 and 1160 illustrated in FIG. 11B and NV NT switchescorresponding to NV NT switches 1205 and 1210 illustrated in FIG. 12A,along pairs of row lines such as X1 and X2. Then, program selectedindividual NV NT switches to a high resistance (erased) state, leavingunselected NV NT switches in a low resistance (erased) state asdescribed further below. Still another method of implementing aconfiguration-setting operation is to selectively modify those NV NTswitches that need to be changed from a low resistance (ON) state to ahigh resistance (OFF) state or from a high resistance (OFF) state to alow resistance (ON) state. In the operation descriptions that follow,the configuration-setting operation examples are based on erasing all NVNT switches to a high resistance (OFF) state and then selectivelyprogramming selected NV NT switches to a low resistance (ON) state.

In this configurable logic configuration-setting operation example, NCLB1320 NT SEL1 circuit is programmed such that select node 1321 is at ahigh voltage enabling logic function (A·B)_(C) output to wire 1323 andNPSM 1340-1 NT SEL2 circuit is programmed such that select node 1341 isat a high voltage which turns FET 1342 to an ON state so that the wire1323 signal is transmitted to wire 1345.

In an erase operation (low-to-high resistance state transition), X1, X2,X3-X8 control lines are set to zero volts and mode select lines Y1, Y2,and Y3 are set to a high voltage such as 2.5 volts to connect all selectnodes, including select nodes 1321 and 1341 to ground. Next, controllines X1 and X2 may be activated using one or more erase pulses V_(E)such that corresponding NV NT switches in NT SEL1 and NT SEL2 are in ahigh resistance state. Note that it is also possible to do a block eraseof all NT SEL circuits. Erase pulses V_(E) are typically in the 5 to 7volt range with relatively fast rise time in nanosecond range.

Next, a programming operation (high-to-low resistance state transition)is performed on NT SEL1 circuit at the intersection of X1, X2, and Y1.In this example, NT SEL 1 select node 1321 is to be in a high voltagestate during NFPGA 1300 logic operation. NT SEL1 operation correspondsto NV NT select circuit 1200 operation and corresponding NV NT switch1205 and 1210 states are set based on NFPGA 1300 operationalrequirements. Therefore, NV NT switch 1205 (FIG. 12A) is programmed to alow resistance state and NV NT switch 1210 is left in a high resistancestate. However, if select node 1321 were to have a low voltage stateduring logic operation then NV NT switch 1205 would be left in a highresistance state and NV NT switch 1210 would be programmed to a lowresistance state.

In a programming operation for NT SEL1, mode line Y1 is set at a highvoltage such as 2.5 volts such that select node 1321 is grounded by anFET corresponding to FET 1215 (FIG. 12A) prior to applying programmingpulses V_(P). Mode lines Y2 and Y3 are set at ground so that selectnodes such as select node 1341 are not held at ground by mode controlFETs such as FET 1215. Next, control line X2 is held at V_(P)/2 andcontrol line X1 is pulsed with programming pulses V_(P) which aretypically in the 3 to 5 volts range with rise times in microsecond rangeand the NV NT switch corresponding to NV NT switch 1205 is programmedfrom a high to low resistance state (from 1 G Ohm to 100 k Ohm forexample). Control line X2 is held at V_(P)/2 so that the NV NT switch inNT SEL1 corresponding to NV NT switch 1210 is not disturbed since onlyV_(P)/2 appears across it and remains in a high resistance state such as1 G Ohm for example, and also so that NV NT switches in adjacent NT SEL2circuit corresponding to NV NT switches NV NT 1205 and 1210 are notdisturbed and remain in a high resistance state. NT SEL2 NV NT switchescorresponding to NV NT switches 1205 and 1210 are not disturbed becausethe difference between voltages on control lines X1 and X2 is applied tothe series combination of two NV NT switches; that isV_(P)−V_(P)/2=V_(P)/2 appears across two NV NT switches in seriescorresponding to NV NT switches 1205 and 1210 because the mode controlFET corresponding to FET 1215 is OFF. Actually, a voltage of V_(P)/2applied to a single NV NT switch is also insufficient to causeswitching. Unselected control line pairs, such as X3-X4; X5-X6, andX7-X8, are held at ground.

Next, in a programming operation for NT SEL2, mode line Y2 is set at ahigh voltage such as 2.5 volts such that select node 1341 is grounded byan FET corresponding to FET 1215 (FIG. 12A) prior to applyingprogramming pulses V_(P). Mode lines Y1 and Y3 are set at ground so thatselect nodes such as select node 1321 are not held at ground by modecontrol FETs such as FET 1215. Next, control line X2 is held at V_(P)/2and control line X1 is pulsed with programming pulses V_(P) which aretypically in the 3 to 5 volts range with rise times in microsecond rangeand the NV NT switch corresponding to NV NT switch 1205 is programmedfrom a high to low resistance state (from 1 G Ohm to 100 k Ohm forexample). Control line X2 is held at V_(P)/2 so that the NV NT switch inNT SEL2 corresponding to NV NT switch 1210 is not disturbed since onlyV_(P)/2 appears across it and remains in a high resistance state such as1 G Ohm for example, and also so that NV NT switches in adjacent NT SEL1circuit corresponding to NV NT switches NV NT 1205 and 1210 are notdisturbed and remain in a high resistance state. NT SEL1 NV NT switchescorresponding to NV NT switches 1205 and 1210 are not disturbed becausethe difference between voltages on control lines X1 and X2 is applied tothe series combination of two NV NT switches; that isV_(P)−V_(P)/2=V_(P)/2 appears across two NV NT switches in seriescorresponding to NV NT switches 1205 and 1210 because the mode controlFET corresponding to FET 1215 is OFF. Actually, a voltage of V_(P)/2applied to a single NV NT switch is also insufficient to causeswitching. Unselected control line pairs are held at ground.

Erase and program operations for NT SEL3 and NT SEL4 circuits correspondto those described with respect to NT SEL 1 and SEL2 circuits exceptthat X3 and X4 control lines are used instead of X1 and X2 controllines. Unselected control line pairs are held at ground.

NCLB 1360 corresponds to NanoLogic™ circuit 1250 illustrated in FIG. 12Dand flip flops and multiplexers (not shown) such as illustrated in FIG.7. An erase operation for NanoLogic™ circuit 1360 NT SEL5 circuit issimilar to the erase operations described above with respect to NT SEL1and NT SEL2. However, in this example, select node 1367 output voltageis selected to be zero so that NOR gate 1365 transmits (C+I)_(C) tooutput OUT of NCLB 1360 so the programming operation is different.

In a programming operation for NT SEL5, mode line Y3 is set at a highvoltage such as 2.5 volts such that select node 1367 is grounded by anFET corresponding to FET 1215 (FIG. 12A) prior to applying programmingpulses V_(P). Mode lines Y1 and Y2 are set at ground so that otherselect nodes (not shown) are not held at ground by mode control FETssuch as FET 1215. Next, control line X7 is held at V_(P)/2 and controlline X8 is pulsed with programming pulses V_(P) which are typically inthe 3 to 5 volts range with rise times in microsecond range and the NVNT switch corresponding to NV NT switch 1205 is programmed from a highto low resistance state (from 1 G Ohm to 100 k Ohm for example). Controlline X7 is held at V_(P)/2 so that the NV NT switch in NT SEL1corresponding to NV NT switch 1210 is not disturbed since only V_(P)/2appears across it and remains in a high resistance state such as 1 G Ohmfor example, and also so that NV NT switches in adjacent NT SEL circuit(not shown) are not disturbed and remain in a high resistance state. NVNT switches (not shown) are not disturbed because the difference betweenvoltages on control lines X7 and X8 is applied to the series combinationof two NV NT switches of any NV SEL circuits that share control lines X7and X8; that is V_(P)−V_(P)/2=V_(P)/2 appears across two NV NT switchesin series because the mode control FET corresponding to FET 1215 is OFF.Actually, a voltage of V_(P)/2 applied to a single NV NT switch is alsoinsufficient to cause switching. Unselected control line pairs are heldat ground.

The programmed NFPGA 1300 logic function is stored in a nonvolatilestate even with no voltage applied to the chip. Voltage may be appliedto the entire chip or routed only to portions of the chip required forlogic operation in order to reduce overall chip power dissipation. Inthe NFPGA 1300 logic operating mode, a low voltage such as ground isapplied to control lines Y1, Y2, and Y3 and a high voltage such as anon-chip voltage of 2.5 volts is applied to control lines X1, X3, X5, andX7 and ground to control lines X2, X4, X6, and X8 (correspondingcontroller logic is not shown). Referring to NV NT select circuit 1200in FIG. 12A, FET 1215 is OFF. If NV NT switch 1205 is programmed to alow resistance state and NV NT switch 1210 is programmed to a highresistance state, then select node 1220 will be at a high voltage stateof 2.5 volts when 2.5 volts is applied to X1 and ground is applied toX2. However, if NV NT switch 1205 is in a high resistance state and NVNT switch 1210 is in a low resistance state, then when 2.5 volts isapplied to X1 and ground is applied to X2, select node 1220 will be atground.

NV SEL1-5 circuits shown in NFPGA 1300 correspond to NV NT selectcircuit 1200 illustrated in FIG. 12A. Programming these switches asdescribed further above with respect to NV NT select circuit 1200results in select nodes 1321, 1341, 1343, and 1358 at high voltage suchas 2.5 volts and select node 1367 at ground. In a logic operation, if Aand B inputs are applied to inputs of NCLB 1320, (A·B)_(C) appears onwire 1323 and since both FET 1342 and 1344 are in an ON state, then(A·B)_(C) is propagated to wire 1345 and then wire 1349; wire 1349 isconnected to the input to multiplexer 1355 which is activated because NTSEL4 NV NT select circuit 1357 has output 1358 at a high voltage of 2.5volts. Therefore, (A·B)_(C) propagates along wire 1362 to NOR gate 1365input I. Because select node 1367 voltage is ground, NOR gate 1365propagates ((A·B)_(C)+C)_(C) to NCLB 1360 output node OUT. The subscript_(C) is used to indicate the complement of a logic term or function.

NCLB Function and Operation Using Nonvolatile Nanotube Select Circuits

NFPGA 1300 illustrated in FIG. 13 illustrates nonvolatile configurablelogic blocks and nonvolatile programmable switch matrices usingrelatively simple examples based on NV NT select circuits and NanoLogic™functions illustrated in FIG. 12. Nonvolatile configurable logic block(NCLB) 1400 illustrates an embodiment of a larger nanotube-based logicfunction corresponding to combinatorial logic function 710 illustratedin FIG. 7 except that flip flop function and multiplexer are not shownin this example. NCLB 1400 is a configurable (programmable) two input(inputs A and B) one output (output F) logic function formed using acascade of FET transfer devices and other logic functions such as NAND,NOR, and a tristate output. The ON or OFF state of each transfer gateand logic operation of some NAND and NOR circuits and the state(tristate or nontristate) of the tristate output driver is controlled bya configuration control logic state (or may be referred to as aconfiguration control bit) supplied by NV NT select circuit nodes. NV NTselect circuits 1410-1, 1410-2, . . . , 1410-7 corresponding to NV NTselect circuit 1150 shown in FIG. 11B and NV NT select circuit 1200shown in FIG. 12A are used to provide nonvolatile configuration controllogic states. The select node logic state of each NV NT select circuitis programmed using X1 and X2 control lines and Y0 to Y6 mode lines asdescribed with respect to FIG. 13. Each select node also includes aninverter where needed so that both true and complement configurationcontrol values are provided for select node outputs. Select node logicstates are nonvolatile and remain unchanged even if power is lost orremoved from the circuit.

NCLB 1400 includes input A to one terminal of FET 1430-1 and input A_(C)formed by inverter 1430-2 and applied to one terminal of FET 1430-3,with the second terminal of each of FETs 1430-1 and 1430-3 dotted andconnected to wire 1430-4 which drives one input of two input NOR gate1440. Inputs A and A_(C) are also connected to one terminal of FET1430-5 and one terminal of FET 1430-6, respectively, with the secondterminal of each of FETs 1430-5 and 1430-6 dotted and connected to wire1430-7 which is connected to one input of three input NAND gate 1450. NVNT select circuit 1410-1 provides configuration control logic state C0on select node 1415-1 output to the gate of FET 1430-1 and C0 _(C)formed by inverter 1420-1 to the gate of FET 1430-3. NV NT selectcircuit 1410-2 provides configuration control logic state C1 on selectnode 1415-2 output to the gate of FET 1430-5 and C1 _(C) formed byinverter 1420-2 to the gate of FET 1430-6.

NCLB 1400 also includes input B to one terminal of FET 1430-8 and inputB_(C) formed by inverter 1430-9 and applied to one terminal of FET1430-10, with the second terminal of each of FETs 1430-8 and 1430-10dotted and connected to wire 1430-11 which drives the second input oftwo input NOR gate 1440. Inputs B and B_(C) are also connected to oneterminal of FET 1430-12 and one terminal of FET 1430-13, respectively,with the second terminal of each of FETs 1430-12 and 1430-13 dotted andconnected to wire 1430-14 which is connected to a second input of threeinput NAND gate 1450. NV NT select circuit 1410-3 provides configurationcontrol logic state C2 on select node 1415-3 output to the gate of FET1430-8 and C2 _(C) formed by inverter 1420-3 to the gate of FET 1430-10.NV NT select circuit 1410-4 provides configuration control logic stateC3 on select node 1415-4 output to the gate of FET 1430-12 and C3 _(C)formed by inverter 1420-4 to the gate of FET 1430-13.

NCLB 1400 also includes NV NT select circuit 1410-5 with select node1415-5 providing output C4 to one input of two input NAND gate 1445. Thesecond input to NAND gate 1445 is supplied by the output of NOR gate1440. NV NT select circuit 1410-6 with select node 1415-6 providesoutput C5 to the third input of three input NAND gate 1450. The outputsof two input NAND 1445 and three input NAND 1450 drive the two inputs ofNOR gate 1455. The output of two input NOR gate 1455 drives the input oftristate inverter 1460. The state of tristate inverter F is controlledby C6 and C6′ which are provided by NV NT select circuit 1410-7. Selectnode 1415-7 provides C6 and inverter 1420-7 provides C6 _(C).

FIG. 14B illustrates eight nonvolatile circuit configurations (CKTCONFIG. #s 1-8) and the corresponding values of C0, C0 _(C), . . . , C5used to generate CKT CONFIG. #s 1-8 for NCLB 1400. FIG. 14B gives anoutput F function based on inputs A and B and the configuration controllogic states. Output F outputs logic values if the C6 state is a logic 1and C6 _(C) is a logic 0. However, if the C6 state is a logic 0 stateand C6 _(C) is a logic 1, then output F remains tristate with no definedvalue. FIG. 15 illustrates equivalent circuits 1500 corresponding to CKTCONFIG. 1-8.

NPSM Function and Operation Using Nonvolatile Nanotube Select Circuits

NFPGA 1300 illustrated in FIG. 13 illustrates configurable logic blocksand programmable switch matrices using relatively simple examples basedon NV NT select circuits and NanoLogic™ functions illustrated in FIG.12. Nonvolatile programmable switch matrix (NPSM) 1600 illustrates anembodiment of a larger nanotube-based routing function corresponding toNPSM 1340-1 and NPSM 1340-2 in FIG. 13. NPSM 1600 is a programmableswitch matrix 1610 with FET transfer gates controlled by select nodeoutputs from NV NT select circuits 1620-1, 1620-2, . . . , 1620-6. PSM1610 is formed by six FET devices to route signals, voltages, currents,or power between any combination of terminals A, B, C, and D. NV NTselect circuits 1620-1, 1620-2, . . . , 1620-6 with corresponding selectnodes 1630-1, 1630-2, . . . , 1630-6 provide corresponding configurationcontrol logic states C1, C2, . . . , C6 to control the OFF or ON stateof each FET in PSM 1610 by providing high voltages such as 2.5 volts foran ON state and a low voltage such as ground for an OFF state.

PSM 1610 includes FET TS1 with terminals connected to terminals C and Dand gate controlled by configuration control logic state C1; FET TS2with terminals connected to terminals A and D and gate controlled byconfiguration control logic state C2; FET TS3 with terminals connectedto terminals A and C and gate controlled by configuration control logicstate C3; FET TS4 with terminals connected to terminals B and D and gatecontrolled by configuration control logic state C4; FET TS5 withterminals connected to terminals A and B and gate controlled byconfiguration control logic state C5; and FET TS6 with terminalsconnected to terminals B and C and gate controlled by configurationcontrol logic state C6.

In operation, the nonvolatile state of select nodes 1630-1 (C1), 1620-2(C2), . . . , 1620-6 (C6) are programmed using control lines X1 and X2and mode lines Y1-Y6 illustrated in FIG. 16. Programming methodscorrespond to those described further above with respect to FIG. 13.After programming, configuration control logic states C1-C6 at eitherhigh voltage such as 2.5 volts or low voltage such as ground are appliedto the gates of the FETs in PSM 1610 and signal routing is established.

Configuration control logic states programmed in NPSM 1600 may be usedto form various routings between terminals A, B, C, and D. Exemplaryinterconnections achievable with NPSM 1600 are listed in Table 2 below.

TABLE 2 Number of FETs in ON State Possible Terminal CombinationsComments One AB, AC, AD, BC, BD, CD Independent paths Two AB & CD, AD &BC, AC & BD Independent paths Three ABC, ABD, ACD, BCD Shared paths FourABCD Shared paths

Nanotube programmable switch matrix NPSM 1600 may be used to routesignals, voltages, currents, and power as described further above withrespect to FIG. 16. Individual FETs included in NPSM 1600 such transfergate FETs TS1-TS6 enable or disable pathways between terminals such asterminals A, B, C, and D. However, transfer gates enable signal,voltage, current, and power flow in both directions, that is betweensource and drain or between drain and source of FET transfer devices. Insome applications, it is desirable to control signal propagationdirection, for example, and bidirectional buffers may be used.Bidirectional buffers may be used in conjunction with NPSMs. Thedirection of signal propagation may be controlled using a controlcircuit. If a nonvolatile control circuit is used, then a signal flowdirection may be set for a particular direction which remains in effecteven if power is removed. The signal flow direction remains the samewhen power is restored. Signal flow direction may be reversed bychanging the state of the nonvolatile control circuit. NPGA 1300illustrated in FIG. 13 nanotube-based bidirectional buffers such as NTBiDi Buffer 1375 control the direction of voltage propagation (andcurrent flow) on wires such as wire 1380. Voltage waveforms propagateleft to right or right to left depending on the nonvolatile state of NTBiDi Buffer 1375 as illustrated further below with respect to FIG. 17.

NT Bidirectional Buffer Function and Operation Using NonvolatileNanotube Select Circuits

FIG. 17A illustrates an embodiment of a nanotube-controlledbidirectional buffer circuit NT BiDi Buffer 1700 which corresponds to NTBiDi Buffer 1375 shown in FIG. 13. The direction of signal flow inbidirectional buffer circuit BiDi Buffer 1710 is controlled by true andcomplement configuration control logic states C and C′ provided by NV NTselect circuit 1715. If C is at ground and C′ is at a positive voltagesuch as 2.5 volts for example, then signal-in on wire 1720-1 andsignal-out on wire 1720-2 is enabled. However, if C is at a positive andC′ is ground, then signal-in on wire 1720-2 and signal-out on 1720-1 isenabled. Signals traveling relatively long distances on global wires mayexperience waveform deterioration in rise and fall time and alsoamplitude. Waveforms of signals flowing between wire 1720-1 and 1720-2or between wire 1720-2 and wire 1720-1 are restored by inverters INV1and INV2 or by inverters INV3 and INV4, respectively.

BiDi Buffer 1710 includes inverter INV1 with input connected to wire1720-1 and to a first terminal of FET T2. The output of INV1 drives theinput of inverter INV2. The output of INV2 is connected to a firstterminal of FET T1 whose gate is controlled by configuration controllogic state C′ supplied by select node 1725-3 of NV NT select circuit1715 through inverter 1725-2. A remaining second terminal of FET T1 isconnected to wire 1720-2 and also to the input of inverter INV3. Theoutput of INV3 drives the input of inverter INV4 whose output drives asecond terminal of FET T2. The gate of FET T2 is controlledconfiguration control logic state C supplied by select node 1725-1 of NVNT select circuit 1715. The first terminal of FET T2 is connected towire 1720-1 and to the input of INV1 as described further above.

NV NT select circuit 1715 may be used to control the direction of signalflow in BiDi Buffer 1710. NV NT select circuit 1715 corresponds to NV NTselect circuit 1150 shown in FIG. 11B and may be programmed and operatedas described with respect to FIG. 11B. NV NT select circuit 1715 alsocorresponds to NV NT select circuit 1200 shown in FIG. 12A and also tothe operation of NT SEL1 circuit as part of in NCLB 1320 shown in FIG.13. Mode control Y may be set to programming mode or to an operatingmode as described further above with respect to FIGS. 11B, 12, and 13and X1 and X2 may be used to program the nonvolatile resistance statesof the NV NT switches. In the operating mode, X1 is set to a highvoltage such as 2.5 volts for example and X2 is set to ground.Configuration control logic state C may be at a high voltage such as 2.5volts and configuration control logic state C′ (complement of C) may beat ground (zero volts). Alternatively, configuration control logic stateC may be at a low voltage such as ground and configuration control logicstate C′ (complement of C) may be at a high voltage such as 2.5 volts.

In operation, NT BiDi Buffer 1700 enables signal flow from wire 1720-1to wire 1720-2 or from wire 1720-2 to wire 1720-1. If C is at ground andC′ is at a positive voltage such as 2.5 volts for example, then FET T2is in an OFF state and FET T1 is in an ON state. A signal arriving onwire 1720-1 propagates through INV1 and INV2 and FET T1 to wire 1720-2.However, a signal arriving on wire 1720-2 can only flow through T1 tothe output node of INV2 and is blocked. Similarly, the signal canpropagate through INV3 and INV4 but is blocked by FET T2 in an OFFstate. Alternatively, if C is at a positive voltage such as 2.5 voltsand C′ is at ground for example, then FET T1 is in an OFF state and FETT2 is in an ON state. A signal arriving on wire 1720-2 propagatesthrough INV3 and INV4 and FET T2 to wire 1720-1. However, a signalarriving on wire 1720-1 can only flow through T2 to the output node ofINV4 and is blocked. Similarly, the signal can propagate through INV1and INV2 but is blocked by FET T1 in an OFF state. A description ofNT-BiDi Buffers similar to NT-BiDi Buffer 1700 may be found in U.S.patent Application No. 61/039,204, filed on Mar. 25, 2008, entitled“Carbon Nanotube-Based Neural Networks and Methods of Making and UsingSame.”

FIG. 17B illustrates an embodiment of a NT enhanced bidirectional buffercircuit NT_E-BiDi Buffer 1740 that not only controls the direction ofsignal flow as does NT BiDi Buffer 1700, but may also be used to invert(or not invert) signal polarity and restore pulses to different (or thesame) voltage amplitudes as described further below with respect to FIG.17B and also with respect to U.S. Patent Application No. 61/039,204,filed on Mar. 25, 2008, entitled “Carbon Nanotube-Based Neural Networksand Methods of Making and Using Same.” Signal flow from wire 1747-1 to1747-2 is processed independently of signal flow from wire 1747-2 to1747-1.

NT_E-BiDi Buffer 1740 circuit is formed by a combination of enhancedbidirectional buffer circuit E-BiDi buffer 1745, NV NT select circuits1750-1, 1750-2 and 1750-3, on-chip voltages V1, V2, V3, and V4 generatedby on-chip programmable voltage generator 1760, and controller 1765.Note that voltages V1, V2, V3, and V4 are supplied to inverters INV1,INV2, INV3, and INV4, respectively, by on-chip programmable voltagegenerator 1760. The operation of on-chip programmable voltage generator1760 is described further below with respect to FIG. 18. The programmingand operation of NV NT select circuits 1750-1, 1750-2 and 1750-3correspond to the programming and operation of NV NT select circuit 1150shown in FIG. 11B, NV NT select circuit 1200 illustrated in FIG. 12A,the operation of NV NT select circuits 1410-1 . . . 1410-7 shown in FIG.14A, and the operation of NV NT select circuits 1620-1 . . . 1620-6shown in FIG. 16.

E-BiDi Buffer 1745 includes inverter INV1 with input connected to wire1747-1 and to a first terminal of FET T2. The output of INV1 drives theinput of inverter INV2. The output of INV2 is connected to a firstterminal of FET T1 whose gate is controlled by configuration controllogic state C1′ supplied by select node 1755-2 inverter INV5 outputwhose input is connected to the NV NT select circuit 1750-1 output node.FET T3 is connected in parallel with INV2 with a first terminalconnected to the output of INV1 and a second terminal connected to afirst terminal of FET T1. The gate of FET T3 is controlled byconfiguration control logic state C2 supplied by select node 1755-4 ofNV NT select circuit 1750-3. A remaining second terminal of FET T1 isconnected to wire 1747-2 and also to the input of inverter INV3. Theoutput of INV3 drives the input of inverter INV4. The output of INV4 isconnected to a first terminal of FET T2 whose gate is controlled byconfiguration control logic state C1 supplied by select node 1755-1 ofNV NT select circuit 1750-1 output node. FET T4 is connected in parallelwith INV4 with a first terminal connected to the output of INV3 and asecond terminal connected to a second terminal of FET T2. The gate ofFET T4 is controlled by configuration control logic state C3 supplied byselect node 1755-3 of NV NT select circuit 1750-2. A remaining secondterminal of FET T2 is connected to wire 1747-1 and also to the input ofinverter INV1.

On-chip voltages V1, V2, V3, and V4 are supplied to E-BiDi Buffer 1745by on-chip nonvolatile nanotube programmable voltage generator 1760 asdescribed further below with respect to FIG. 18. V1 (and V2, V3, and V4)may be varied over a relatively large range of voltages (0 to 5 volts,for example). Controller 1765 outputs O₁ . . . O_(M) are inputs toon-chip NV NT programmable voltage generator 1760 used to program thevalues of V1, V2, V3, and V4 as described further below with respect toFIG. 18. Controller 1765 also controls the programming and operation ofNV NT select circuits 1750-1, 1750-2, and 1750-3 to control the logicaloperation of E-BiDi Buffer 1745 with outputs X1, X2, Y1, Y2, and Y3connected to corresponding NV NT select circuits that control the logicoperation of NT_E BiDi buffer 1740. Inputs I₁ . . . I_(N) to controller1765 are processed by the controller 1765 logic (not shown).

In operation, NT BiDi Buffer 1740 enables non-inverted signal flow fromwire 1747-1 to wire 1747-2 or from wire 1747-2 to wire 1747-1 if FET T3and FET T4 are in an OFF state. If C1 is at ground and C1′ (logicalcomplement of C1) is at a positive voltage such as 2.5 volts forexample, then FET T2 is in an OFF state and FET T1 is in an ON state. Asignal arriving on wire 1747-1 propagates through INV1 and INV2 and FETT1 to wire 1747-2. However, a signal arriving on wire 1747-2 can onlyflow through T1 to the output node of INV2 and is blocked. Similarly,the signal can propagate through INV3 and INV4 but is blocked by FET T2in an OFF state. Alternatively, if C1 is at a positive voltage such as2.5 volts and C1′ is at ground for example, then FET T1 is in an OFFstate and FET T2 is in an ON state. A signal arriving on wire 1747-2propagates through INV3 and INV4 and FET T2 to wire 1747-1. However, asignal arriving on wire 1747-1 can only flow through T2 to the outputnode of INV4 and is blocked. Similarly, the signal can propagate throughINV1 and INV2 but is blocked by FET T1 in an OFF state.

In operation, on-chip voltage V1 is applied to the inverter INV1 and V2is applied to inverter INV2 PFET source terminal. Voltages V1 and V2 maybe varied over a range of voltages from 0 to 5 volts for example byon-chip NV NT programmable voltage generator 1760. In the case of anon-inverting signal transmission, FET T3 is in OFF state and voltagesV1 and V2 may be varied from 1 to 5 volts for example. However, in aninverting operation, voltage V2 is reduced to zero to enable FET T3turn-ON. V1 may be set in the 1 to 5 volts range and the signal flowingfrom wire 1747-1 to wire 1747-2 will be inverted and its amplitude mayremain the same or may be modified.

In operation, on-chip voltage V3 is applied to the inverter INV3 and V4is applied to inverter INV4 PFET source terminal. Voltages V3 and V4 maybe varied over a range of voltages from 0 to 5 volts for example byon-chip NV NT programmable voltage generator 1760. In the case of anon-inverting signal transmission, FET T4 is in OFF state and voltagesV3 and V4 may be varied from 1 to 5 volts for example. However, in aninverting operation, voltage V4 is reduced to zero to enable FET T4turn-ON. V3 may be set in the 1 to 5 volts range and the signal flowingfrom wire 1747-2 to wire 1747-1 will be inverted and its amplitude mayremain the same or may be modified.

FIG. 18 illustrates an embodiment of a nonvolatile nanotube-controlledon-chip programmable voltage generator circuit (NV NT programmablevoltage generator 1800) NT_V-GEN 1800 that corresponds to on-chip NV NTprogrammable voltage generator 1760 illustrated in FIG. 17B. On-chipvoltage regulator 1810 is connected to a power source at voltage V_(DD)and generates an on-chip voltage V_(O-C) on output node 1830 whenprovided with a reference voltage V_(REF) on first input terminal 1835.Differential amplifier 1815 holds output voltage V_(O-C) on output node1830 equal to reference voltage V_(REF). Differential amplifier 1815operation is similar to the operation of differential amplifiersdescribed in R, Jacob Baker et al., “CMOS circuit Design, Layout, andSimulation,” IEEE Press, 1998, p. 579-592. Regulated output voltageV_(O-C) and corresponding output current to on-chip circuits is suppliedby PFET 1825 typically having a wide channel width (width-to-lengthratio of 100:1 or more for example). Inverter 1820 provides outputvoltage feedback to a second input terminal 1880 of differentialamplifier 1815. A reference voltage is supplied to a first inputterminal 1835 of differential amplifier 1815 by nanotube-controllednonvolatile nanotube voltage reference generator NT_R-GEN 1840. NT_R-GEN1840 includes NV NT select circuit 1845 with reference node connected tofirst input terminal 1835. A pair of NV NT switches is programmed to aratio of ON resistance values (states) that sets reference voltageV_(REF) based on a ratio of NV NT resistor values. In this application,NV NT switches are used in an analog mode and both NV NT switches aretypically in an ON state of different resistance values and are referredto NANRISTORS in which ON resistance values are held in a nonvolatilestate. NV NT select circuit 1845 includes NANRISTORS 1850 and 1855sharing common first nodes which forms a select node that generatesV_(REF) on the first input terminal 1835 of differential amplifier 1815.FET 1860 is a mode control FET which is ON during programming and OFFduring operation as described further above with respect to NV NT selectcircuit 1150 in FIG. 11B for example. PFET 1865 has one terminalconnected to a second node of NANRISTOR 1850 and a second terminalconnected to a power source at voltage V_(DD). NFET 1870 has oneterminal connected to a second node of NANRISTOR 1855 and a secondterminal connected to a reference voltage such as ground. The gatevoltage of PFET 1865 is controlled by reference voltage controller 1875output G1; the gate of FET 1870 is controlled by output G2, and mode Youtput to the gate of FET 1860 selects program or operate modes. X1 andX2 provide programming (program and erase) pulses as described furtherabove with respect to FIG. 11B.

In a programming operation, G1 is at a high voltage such as 2.5 voltsfor example and PFET 1865 is OFF and G2 is at ground and NFET 1870 isOFF. Y is at a high voltage such as 2.5 volts for example and NFET 1860is ON and the select node connected to first input terminal 1835 is atground. X1 and X2 apply pulses to the second terminals of nonvolatileNANRISTORS 1850 and 1855 and resistor values are adjusted such that aratio of NANRISTOR 1850 and 1855 values results in a voltage V_(REF)when V_(DD) is applied during NT_R-GEN 1840 operation. Programmingcorresponds to programming as described with respect to NV NT selectcircuit 1150 in FIG. 11B. All pulses are controlled by reference voltagecontroller 1875 based on inputs IN₁ . . . IN_(M) which correspond to O₁. . . O_(M) in FIG. 17B.

In a reference voltage setting operating mode, Y is at ground and NFET1860 is OFF. X1 and X2 are tristated. G1 is a ground such that PFET 1865is ON and connects a second terminal of NANRISTOR 1850 to V_(DD). G2 isat a high voltage such as 2.5 volts such that NFET 1870 is ON. PFET 1865and NFET 1870 are designed such that the FET ON channel resistance isnegligibly small compared to NANRISTOR 1850 and 1855 resistance valueswhich may be in 100 k Ohm to 10M Ohm range for example. Higher NANRISTORvalues result in less current flow during operation. Also, sinceNANRISTOR values are nonvolatile, power may be removed from portions ofchips not in use.

In operation, V_(REF) is determined as follows

V _(REF) =R _(NANRISTOR 1855) ×V _(DD)/(R _(NANRISTOR 1850) +R_(NANRISTOR 1855))

Note: if R_(NANRISTOR 1850)=R_(NANRISTOR 1855) , V _(REF) =V _(DD)/2

V_(REF) at first input terminal 1835 of differential amplifier 1815 isset equal to the desired voltage level for V_(O-C) and the output node1830 of differential amplified 1815 which also corresponds to outputnode 1830 of NT_V-GEN 1800 is held at V_(O-C) even as circuit load atoutput 1830 is varied (draws more or less current). NT_V-GEN 1800circuit output V_(O-C) corresponds to one of voltage outputs V1, V2, V3,and V4 shown in FIG. 17B. The number of NT_V-GEN 1800 circuits neededdepends on the number of on-chip voltages to be generated.

NV NT Bidirectional Buffer Function and NV NT Programmable VoltageGenerator Used to Generate Precision Timing (Delay) and for PowerManagement

Nonvolatile nanotube programmable voltage (NT_V-GEN) 1800 shown in FIG.18 may be used to generate and control on-chip voltage to variouscircuits in an integrated circuit chip such as nonvolatile nanotubebidirectional buffer (NT_E-BiDi Buffer) 1740 shown in FIG. 17B forexample. CMOS circuits, as is well known in the industry, swing fromrail-to-rail and operate over a wide range of voltages. CMOS circuitswith threshold voltages of 0.7 volts, for example, in the range of 1 to3.5 volts for example but at varying speeds and power dissipation. Ifthe operating voltage is low, approaching 1 volt for example, then CMOScircuits will operate more slowly due to reduced overdrive but also willdissipate less power. However, CMOS circuits will operate at high speedif the circuit is operated at a higher voltage such as 3.5 volts forexample. Switching CMOS circuits dissipate power proportional to f·C·V²,where f is the frequency of operation, C is the capacitive load,typically primarily due to wiring capacitance, and the square of therail-to-rail voltage swing V.

Controller 1765 is described above with respect to control of voltagesV1-V4 applied to NT_E-BiDi Buffer 1740 to modify the amplitude andpolarity of pulses between input and output of NT-E-BiDi Buffer 1740.However, by controlling the voltage applied to NT_E-BiDi Buffer 1740,controller 1765 also varies power dissipation and delay through thebuffer circuit.

Controller 1765 may be used to vary voltages applied to NT_E-BiDi Buffer1740 to achieve continuous precision timing (delay) control becausevarying CMOS voltage can be used to control delay through CMOS circuitsas described further above. Bertin et al U.S. patent application Ser.No. 11/835,583, filed on Aug. 8, 2007, entitled “Latch Circuits andOperation Circuits Having Scalable Nonvolatile Nanotube Switches asElectronic Fuse Replacement Elements,” U.S. patent application Ser. No.11/835,612, filed on Aug. 8, 2007, entitled “Nonvolatile ResistiveMemories Having Scalable Two-Terminal Nanotube Switches,” precisiontiming (delay) control in discrete steps until a pulse appears in avalid data window defined by a strobe pulse. In this case, pulse timing(delay) NT_E-BiDi buffer 1740 circuit may be monitored by sensing forthe presence or absence of an output pulse in a valid data windowdefined by a strobe pulse. Voltages are adjusted by NT_V-GEN 1800, underthe control of controller 1765, until the output pulse is detected by acomparator circuit (not shown) and a signal is sent to controller 1765.Reference voltage generator 1875, based on inputs from controller 1765or another signal source, incrementally changes the ratio of theresistance values of Nanristors 1850 and 1855 in NT_R-GEN 1840 (asdescribed further above) until the output voltage of NT_V-GEN 1840circuit (or circuits since there may be more than one used) results inthe desired timing speed (delay). At this point Nanristor 1850 and 1855nonvolatile resistance values are left unchanged. As a consequence ofthis method of continuous speed (delay) adjustment, the amplitude of thesignal output may be different to that of the signal input. Theamplitude may be restored to a full rail-to-rail swing of, for example,3.5 volts may be restored by sending the signal through one or moreinverter stages (not shown). Delays introduce by inverter(s) are inseries with the signal path and will be included in the adjustedprecision timed waveform.

Power management (control of power dissipation) may be implemented forvarious regions of a chip (or the entire chip) by reducing the on-chipvoltage output of NT_R-GEN 1840. This may be achieved by inputs to thereference voltage controller 1875 and corresponding adjustment of thevalues of nanristors 1850 and 1855 as described further above withrespect to signal speed (delay) timing control. A power reduction signalmay be provided to chips by the system by an OP-Code to a detector asdescribed further below. Alternatively, a temperature sensor may belocated on-chip that sends a signal to a controller such as referencecontroller 1875 to reduce operating voltage which reduces powerdissipation.

NV NT Bidirectional Buffer Function and/or NV NT Programmable VoltageGenerator Used as Security Event Response Functions

In the event that a security event is detected, the operation ofNT_E-BiDi buffer 1740 and NT_V-GEN 1800 may be changed. For example,voltages such V1-V4 may be driven to zero and switching operationsterminated. Alternatively, voltages may be changed, amplitudes,polarities, timings (delays) may be modified to conditions that do notreflect the correct operating conditions of the application.

One method of detecting a security event is to use an on-chip detectorthat monitors an OP-Code stream and detects a security event (alarm)code as described in Bertin et al. U.S. Pat. No. 7,394,687. Oncedetected, programmable wiring and programmable logic and signal routingcircuits may be modified as described further so that the highapplication function security is changed and therefore protected.

Nanotube Configurable Logic Blocks (NT_CLB) & Nanotube ProgrammableSwitch Matrix (NT_PSM) Using Nonvolatile NRAM-Controlled Select Circuits

Various NRAM™ memory architectures are combined with CLB and PSMfunctions to form NCLB and NPSM building blocks that may be integratedto form NFPGA logic as described with respect to FIGS. 19-26 illustratedfurther below.

NFPGA Function and Operation Using NRAM™s

Nonvolatile NRAM™ array schematic 1900 includes a matrix of 16nonvolatile storage cells C00, C01, . . . , C33 as illustrated in FIG.19. NRAM™ memory architecture and operation are described in U.S. patentapplication Ser. No. 11/280,786, filed on Nov. 15, 2005, entitled“Two-Terminal Nanotube Devices and Systems and Methods of Making,” U.S.patent application Ser. No. 11/274,967, filed on Nov. 15, 2005, entitled“Memory Arrays Using Nanotube Articles with Reprogrammable Resistance,”U.S. patent application Ser. No. 11/835,583, filed on Aug. 8, 2007,entitled “Latch Circuits and Operation Circuits Having ScalableNonvolatile Nanotube Switches as Electronic Fuse Replacement Elements,”U.S. patent application Ser. No. 11/835,612, filed on Aug. 8, 2007,entitled “Nonvolatile Resistive Memories Having Scalable Two-TerminalNanotube Switches,” and U.S. patent application Ser. No. 11/835,613,filed on Aug. 8, 2007, entitled “Memory Elements and Cross PointSwitches and Arrays of Same Using Nonvolatile Nanotube Blocks,” and arehereby incorporated by reference. Each memory cell illustrated in NRAM™array schematic 1900, such as representative cell C00, includes a selecttransistor T00 that may be an NFET as shown, or may also be a PFET (notshown) or a CMOS transfer device (not shown) that includes both NFET andPFET devices, or other types of switching devices (not shown) such asdiode steering devices as described in U.S. patent application Ser. Nos.11/835,651, 11/835,759, 11/835,845, 11/835,852, 11/835,856, 11/835,865,each filed on Aug. 8, 2007, entitled “Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods of MakingSame.” Each cell, such as cell C00, also includes a nonvolatile nanotubestorage node NT00 such as NV NT switch 1110 as illustrated by NRAM™ cell1100 in FIG. 11A. Nonvolatile nanotube storage node NT00 (NV NT storagenode) may be formed using NV NT switch-types or NV NT block switch-typesillustrated further above and summarized in FIGS. 10B, 10C and 10D,respectively.

Nonvolatile storage cells such as cell C00 are formed by connecting thesource SC00 of a transistor such as NFET T00 to a first terminal of a NVNT storage node such as NV NT storage node NT00 illustrated in FIG. 19.NRAM™ array schematic 1900 is formed by connecting word lines WL0, WL1,WL2, and WL3 to corresponding gates of NFET select transistors incorresponding storage cells; connecting secondary word lines WWL0, WWL1,WWL2, and WWL3 (typically used as reference lines connected to a voltagesuch as ground (zero volts)) to corresponding second terminals of NV NTstorage nodes in corresponding storage cells; and connecting bit linesBL0, BL1, BL2, and BL3 to corresponding drain diffusions ofcorresponding NFET select transistors in corresponding nonvolatilestorage cells as illustrated in FIG. 19. For example, word line WL0 isconnected to the gate of NFET T00 by contact GC00; secondary word lineWWL0 is connected to the second terminal of nonvolatile nanotube storagenode NT00 by contact NC00; and bit line BL0 is connected to the drain ofNFET T00 by contact DC00.

In erase and programming operations, a word line such as word line WL0is selected and FETs C00, C01, C02, and C03 are turned ON. Word linesWL1, WL2, and WL3 are kept at ground and all other FETs are in an OFFstate. In an erase (write “0”) operation, bit lines are pulsed in therange of 5 to 7 volts with rise times in the nanosecond range using oneor more pulses. One approach is to erase all bits along selected wordline WL0 so that all NV NT switches are in a high resistance (OFF) statecorresponding to a logical “0” state. Next, selected cells along WL0 areprogrammed to a low resistance (ON) state corresponding to a logical “1”state. So for example, if cell C00 is to store a low resistance value, aprogram (write “1”) operation is performed in which bit line BL0 ispulsed in the range of 3-5 volts with rise times in the microsecondrange using one or more pulses. If cells C01, C02, and C03 are to remainin a high resistance logical “0” state, then bit lines BL1, BL2, and BL3are held at ground.

In read operating mode, bit lines such as BL0, BL1, BL2, and BL3 areprecharged to a voltage such as 2.5 volts for example. A word line suchas word line WL0 is selected and select FETs in NRAM™ cells C00, C01,C02, and C03 are turned ON. In this example, cell C00 is in a lowresistance state corresponding to a logical “1” state and bit line BL0is discharged and a logical “1” state will sensed and latched. Sincecells C01, C02, and C03 are in a high resistance state, bit lines BL1,BL2, and BL3 will not discharge and a logical “0” state will be sensedand latched. In a ×4 NRAM™ configuration, all 4 bits are provided at theNRAM™ memory output. In a ×1 NRAM™ configuration, 1 of 4 bits isselected and provided at the NRAM™ memory output.

FIG. 6 illustrates CLB 600 which includes look up table (LUT) 610. LUT610 is described further above with respect to FIG. 6 which correspondsto LUTs as described in U.S. Pat. Re. 34,363 Jun. 24, 1991 Ross Freemanin which a 16 bit RAM (a volatile SRAM) in a ×1 configuration is used togenerate LUT 610 logic look up table. An NRAM™ may be used instead asthe RAM function. An NRAM™ has the advantage of smaller array sizebecause of smaller cell size and nonvolatile operation. FIG. 20illustrates NCLB 2000 including NLUT 2010 that includes 16 bit NRAM™array 2015 that corresponds to NRAM™ array schematic 1900 describedfurther above with respect to FIG. 19. Inputs I₁ and I₂ to X-Decoder2020 and I₃ and I₄ to Y-Decoder 2025 select one of 16 bits to output towire 2030. NLUT 2010 output drives wire 2030 which in turn drives aninput to D flip flop 2035, which also includes a clock input, and alsodrives a first terminal of multiplexer (MUX) 2040. A second terminal ofMUX 2040 is driven by the output of D flip flop 2035. MUX 2040 driveswire 2045 providing NCLB 2000 output O.

FIG. 21 illustrates a block diagram of an embodiment of NFPGA 2100formed using NRAM™ controlled NCLBs such as NCLB 2120 and NRAM™controlled NPSMs such as NPSM 2140-1. NFPGA 2100 also includes aNanoLogic™ circuit that includes a nonvolatile nanotube select circuit(labeled NT SEL) that forms nanotube configurable logic block NCLB 2160and an NRAM™ controlled MUX 2155 as part of NCLB 2150. NRAM™ controlledbidirectional buffers (not shown) may also be included. Flip flops andmultiplexers (shown in FIGS. 6 and 7) may be included as well.

The NFPGA 2100 logic function is configured using NRAM™ memories (ormemory sub-arrays) NRAM1-NRAM4 whose operations are described furtherabove with respect to FIGS. 19 and 20. In addition to NRAM™s, NCLB 2160programming also includes NV NT select circuit NT SEL as shown in FIG.21 and described further above with respect to FIG. 13 using program andoperation inputs X1, X2, and mode control input Y. Multiplenanotube-configurable logic blocks (NCLBs) and nanotube programmableswitch matrices (NPSMs) are configured (programmed) and determine NFPGA2100 logic function.

NCLB 2120 corresponds to NCLB 2000 illustrated in FIG. 20 that mayinclude flip flops and multiplexers (not shown) such as illustrated inFIG. 6; NPSM 2140-1 uses NRAM2 output 2141 to control the ON/OFF stateof FET 2142; NPSM 2140-2 uses NRAM3 output 2143 to control the ON/OFFstate of FET 2144; NCLB 2160 corresponds to NanoLogic™ circuit 1270illustrated in FIG. 12D and flip flop and multiplexers (not shown) suchas illustrated in FIG. 7; NCLB 2150 includes NRAM4 whose output 2158controls the operation of multiplexer 2155 and may include flip flopsand other multiplexers (not shown) as illustrated in FIG. 7. CLBfunctions such as 2105 and 2170 may include configurable logic functionssuch as illustrated in FIGS. 6 and 7 which may or may not include NRAM™and NanoLogic™ functions. Wiring region 2110 shows horizontal wires thatmay be used for various interconnections (not shown). NT BiDi Bufferscontrolled by NRAM™s (not shown) may be used to controls the directionof signal flow on selected wires as explained further above with respectto FIGS. 17A and 17B. Using said NT BiDi Buffers, configuration controllogic states (may also be referred to as configuration control bits) aresupplied by NRAM™ memory outputs.

In logic configuration setting operations for NCLB 2120, NCLB 2150, NPSM2140-1 and NPSM 2140-2, NRAM1-NRAM4 are programmed as described withrespect to NRAM™ array schematic 1900 (FIG. 19) and NRAM™ array 2015 byword and bit line waveforms selected by X-decoder 2020 and Y-decoder2025 (FIG. 20) to generate nonvolatile logic voltages that controldevice ON/OFF states and control logic block functions. NCLB 2160 logicfunction is determined by NT SEL based on inputs X1, X2, and Y asdescribed further above with respect to FIG. 11B, FIG. 12A, and FIG. 13for example.

In this logic configuration setting operation example, NCLB 2120 logicfunction includes NLUT 2122 with NRAM1 corresponding to FIG. 20 withNLUT 2122 programmed such that a logic function such as (A·B)_(C) (thecomplement of A logically ANDed with B) for example is outputted to wire2123 and NPSM 2140-1 NRAM2 is programmed such that output 2141 is at ahigh voltage which turns FET 2142 to an ON state so that the wire 2123signal is transmitted to wire 2145. NPSM 2140-2 NRAM3 is programmed suchthat output 2143 is at a high voltage which turns FET 2144 to an ONstate so that the wire 2145 signal is transmitted to wire 2149. NCLB2150 NRAM4 is programmed such that output 2158 activates MUX 2155 whichis connected to wire 2149 and transmits the signal on wire 2149 to wire2162.

NCLB 2160 corresponds to NanoLogic™ circuit 1250 illustrated in FIG. 12Dand flip flops and multiplexers (not shown) such as illustrated in FIG.7. Three input NOR gate 2165 has a first input controlled by the selectnode 2167 output of NT SEL. Input I corresponds to the signal on wire2162 and is applied to a second input of NOR gate 2165. Input C isapplied to a third input of NOR gate 2165. In this example, select node2167 output voltage is selected to be zero so that NOR gate 2165transmits (C+I)_(C) to output OUT of NCLB 2160. With FPGA 2100 NRAM™ andNV NT select circuits programmed as described in this example, (A·B)_(C)appears on wire 2123 and since both FET 2142 and 2144 are in an ONstate, then (A·B)_(C) is propagated to wire 2145 and then to wire 2149;wire 2149 is also an input to multiplexer 2155 which is activatedbecause NRAM4 has output 2158 at a high voltage such as 2.5 volts.Therefore, (A·B)_(C) propagates along wire 2162 to NOR gate 2165 inputI. Because select node 2167 voltage is ground, NOR gate 2165 propagates((A·B)_(C)+C)_(C) to NCLB 2160 output node OUT.

NCLB Function and Operation Using NRAM™s

NFPGA 2100 illustrated in FIG. 21 illustrates nonvolatile configurablelogic blocks and nonvolatile programmable switch matrices usingrelatively simple examples based on NRAM™s illustrated in FIGS. 19 and20. One nonvolatile configurable logic block based on a nonvolatilenanotube select circuit as described further above with respect to FIG.12D is also included to illustrate the ability to mix NRAM™-based and NVNT select circuit-based approaches to nonvolatile configurable logicblocks in the same NFPGA design. Since nonvolatile configurable logicblocks have been described further above with respect to FIGS. 13 and14, the emphasis is on NRAM™-controlled programmable logic functions.FIGS. 22A and 22B described further below illustrate NRAM™ architecturesthat provide NRAM™-generated configurable control bits (corresponding toconfigurable control logic states) based on bit configurations stored inNRAM™ arrays similar to NRAM™ array schematic 1900 in FIG. 19.

NRAM™ architectures may be similar to the NRAM™ architecture describedwith respect to NCLB 2000. NCLB 2000 is illustrated further above withrespect to FIG. 20 and includes an NRAM™ memory used to realizenonvolatile look up table (NLUT) 2010 which provides configurationcontrol logic states (or configuration controlled bits) as partnonvolatile programmable logic block (NCLB) 2000 function. NRAM™architectures may also be designed to provide multi-bit outputs inparallel and may use fewer on-pitch circuits to implement NCLB functionsin a smaller physical area for example as illustrated further below byNRAM™ 2200 in FIG. 22, and configured to provide nonvolatileconfiguration control bits.

FIG. 22A illustrates an embodiment of NRAM™ 2200 architecture shown inschematic form that may be used as an NRAM™-based nonvolatile controlbit generator that provides true and complement control bit outputs.NRAM™ 2200 includes NV memory array 2205 shown in schematic form whichcorresponds to nonvolatile NRAM™ array schematic 1900 illustrated inFIG. 19, but with only one word line and six parallel bit lines.Controller 2210 accepts inputs 2212 and generates outputs O1-O10.Outputs O1-O6 drive a first input of two terminal tristate AND gates2215-1 to 2215-6, respectively. Output O7 drives second input gates oftwo terminal tristate AND gates 2215-1 to 2215-6 to enable or disablebit line selection for program or erase operations. Outputs of twoterminal tristate AND gates 2215-1 to 2215-6 drive bit lines BL1-BL6,respectively. Bit lines BL1-BL6 are also connected to the drain ofcorresponding NFET select transistors shown in NV memory array 2205. Aword line WL1 is connected to the output of word line driver WL DR whichis driven by output 09 of controller 2210. Word line driver WL DR drivesarray word line WL1 which is connected to gates of FET select devicesshown in NV memory array 2205 for cells B11, B12, . . . , B16. Storagenodes may be formed using NV NT switches or NV NT blocks as describedfurther above with respect to FIGS. 10B, 10C and FIG. 10D, respectively.Each first terminal of a NV NT switch or a NV NT block is connected to asource of a corresponding select FET and a second terminal is connectedto a common reference line such as reference line REF which may beconnected to ground. PFETs 2220-1 to 2220-6 have first terminalsconnected to a voltage source V. Each second terminal of PFETs 2220-1 to2220-6 is connected to bit lines BL1-BL6, respectively, and gateterminals are connected to a common control line which is connected tocontroller 2210 output O8 which enables or disables read operations. Bitlines BL1-BL6 are also connected to a first terminal of each transferNFET 2225-1 to NFET 2225-6 transfer devices, respectively. A secondterminal of each transfer device NFET 2225-1 to NFET 2225-6 drives aninput of inverters INV1′-INV6′, respectively, and the gates of transferdevices NFET 2225-1 to NFET 2225-6 are connected to a common controlline which is driven by output O10. The outputs of inverters INV1′-INV6′provide complement configuration control bits C₁′-C₆′. The outputs ofinverters INV1′-INV6′ also drive inputs of inverters INV1-INV6,respectively, whose outputs generate configuration control bits C1-C6,respectively. Note that the complement of a logic (or bit) variable maybe indicated as C′ or C_(C) for example. Both forms are usedinterchangeably throughout the specification. NRAM™ 2200 configurationcontrol bits C1-C6 and complement configuration control bits C1′-C6′ maybe used as part of NCLB 2300 illustrated further below in FIG. 23 andmay also be used as part of NPSM 2400 illustrated further below withrespect to FIG. 24.

FIG. 22B illustrates an embodiment of NRAM™ 2250 in schematic form whichcorresponds to NRAM™ 2200 but with a larger 6×K nonvolatile memory array2205′ compared with 1×6 nonvolatile memory array 2205. Additional worddrivers, word driver input, and output lines have been added to NRAM™2200 to accommodate the larger memory array. Word line driver WL DR withinput O9 driving word line WL1 has been replaced with word line driversWL DR1 to WL DRK with corresponding inputs O9-1 to O9-K andcorresponding outputs driving word lines WL1-WLK, respectively. Wordline WL1 drives gates of select FET transistors in cells B11-B16; otherword lines (not shown) drive corresponding gates of select FETtransistors in other cells; and word line WLK drives gates of select FETtransistors in cells BK1-BK6. All other functions are unchanged and areas described with respect to FIG. 22A.

Referring to FIG. 22A, in erase and program operations, controlleroutput O8 is held at a high voltage such as 2.5 volts and PFETs 2220-1to 2220-6 are OFF. Transfer NFETs 2225-1 to 2225-6 gates are held atground (zero volts) by O10 and are in an OFF state. Two input tristatingAND gates 2215-1 to 2215-6 are activated by O7 at a high voltage such as2.5 volts which disables tristate and enables two input AND gateoperation. At this time, erase and/or program NRAM™ operations may beperformed as described further above with respect to FIG. 19. Once NV NTswitches (or NV NT blocks) in NV memory array 2205 cells have beenswitched to ON or OFF states, erase and program operations areterminated and a nonvolatile high resistance state (OFF) or anonvolatile low resistance state (ON) is stored. A high resistance statemay correspond to a logic “0” state and a low resistance state maycorrespond to a logic “1” state for example. NV memory array 2205 cellsare in the following states as illustrated in FIG. 22A. B11 is in a highresistance state; B12 is in a low resistance state; B13, B14, and B15are in high resistance states, and B16 is in a low resistance state.

Referring to FIG. 22A, in a read operation, controller output O7 is atground and two input tristate AND gates 2215-1 to 2215-6 are inactiveand tristated. Controller output O8 is at ground and PFETs 2220-1 to2220-6 are ON. PFETs are designed for a high ON channel resistancevalues using minimum widths and greater than minimum lengths. Thereforevoltage V is applied through a channel resistance of 1M Ohm for example.A read voltage is applied by WL DR to word line WL1 and all select FETsare turned ON. In cells with NV NT switches (or NV NT blocks) are in ahigh resistance state, typically 1 G Ohm and higher, the output voltageon the corresponding bit lines is V. If however, the series combinationof select FET ON resistance and NV NT switch ON resistance is 100 k Ohmsor less, then the voltage on the corresponding bit lines will be at alow voltage at V/10 or less. With transfer NFETs 2225-1 to 2225-6 heldin an ON state by controller output O10 at a high voltage such as 2.5volts, bit line BL1-BL6 voltages are applied to inverters INV1′-INV6′,respectively, generating complement configuration control bits C1′-C6′;and INV1′-INV6′ outputs drive corresponding inverters INV1-INV6generating configuration control bits C1-C6, respectively. In the NRAM™2200 example with NV memory array 2205 cells programmed as illustratedin FIG. 22A configuration control bit (true and complement) outputsduring a read operation are as follows: C1′, C2, C3, C4, C5′ and C6 areat a high voltage such as 2.5 volts for example; C1, C2′, C3′, C4′, C5,and C6′ are at a low voltage such as ground.

Referring to FIG. 22B, erase and program operations are as describedwith respect to FIG. 22A for each of the word lines WL1 . . . WLK. Also,read operations are as described with respect to FIG. 22A for each ofthe word lines WL1 . . . WLK. Bits B11, B12, . . . , B16 in FIG. 22B arein the same state as bits B1-B6 in FIG. 22A. However, bits BK1-BK6states are not all the same. Therefore, in the NRAM™ 2250 exampleillustrated in FIG. 22B, NV memory array 2205′ word line WLKconfiguration control bit (true and complement) outputs during a readoperation are as follows: C1, C2′, C3, C4′, C5 and C6′ are at a highvoltage such as 2.5 volts for example; C1′, C2, C3′, C4, C5′, and C6 areat a low voltage such as ground.

In read operations, the logic state (logic “1” or logic “0”) ofconfiguration control bits illustrated in FIG. 22B may be rapidlychanged between multiple pre-programmed states stored in NRAM™ 2205′ toreconfigure programmable logic functions for reconfigurable computingoperation. In order to maximize reconfigurable computing speed, apipelined memory operating mode architecture such as used in high speedmemory cache operations may be used in which a new set of configurationcontrol bits may be generated during each clock cycle after an initiallatency (read access time) delay of multiple clock cycles. If the logicfunction or routing matrix to be programmed has the requiredconfiguration stored in NRAM™ arrays, then for relatively small NRAM™arrays, configuration control bits (true and complement) may be changedin cycle times of 150 ps corresponding to clock frequencies of 6.7 GHzfor example for a 90 nm technology node when corresponding NRAM™ arraysare operated in a pipelined architecture.

Nonvolatile nanotube configurable logic block (NCLB) 2300 illustrates anembodiment of a larger nanotube-based logic function corresponding tocombinatorial logic function 710 illustrated in FIG. 7 except that flipflop function and multiplexer are not shown in this example. NCLB 2300is a nanotube configurable (programmable) two input (inputs A and B) oneoutput (output F) logic block (function) formed using a cascade of FETtransfer devices and other logic functions such as NAND, NOR, and atristate output and is similar to the logic function illustrated in FIG.14A. The ON or OFF state of each transfer gate and logic operation ofsome NAND and NOR circuits is controlled by a configuration control bit(which may also be referred to as a configuration control logic state)supplied by NRAM™ output bits. NRAM™ 2310 is used to generate true andcomplement configuration control bits C0, C0′, C1, C1′, . . . C6, andC6′. NRAM™ 2310 corresponds to NRAM™ 2200 shown in FIG. 22A or NRAM™2250 shown in FIG. 22B.

NCLB 2300 includes input A to one terminal of FET 2330-1 and input A_(C)formed by inverter 2330-2 is applied to one terminal of FET 2330-3, withthe second terminal of each of FETs 2330-1 and 2330-3 dotted andconnected to wire 2330-4 which drives one input of two input NOR gate2340. Inputs A and A_(C) are also connected to one terminal of FET2330-5 and one terminal of FET 2330-6, respectively, with the secondterminal of each of FETs 2330-5 and 2330-6 dotted and connected to wire2330-7 which is connected to one input of three input NAND gate 2350.NRAM™ 2310 provides configuration control bits C0 to the gate of FET2330-1 and C0′ to the gate of FET 2330-3. NRAM™ 2310 providesconfiguration control bits C1 to the gate of FET 2330-5 and C1′ to thegate of FET 2330-6.

NCLB 2300 also includes input B to one terminal of FET 2330-8 and inputB_(C) formed by inverter 2330-9 and applied to one terminal of FET2330-10, with the second terminal of each of FETs 2330-8 and 2330-10dotted and connected to wire 2330-11 which drives the second input oftwo input NOR gate 2340. Inputs B and B_(C) are also connected to oneterminal of FET 2330-12 and one terminal of FET 2330-13, respectively,with the second terminal of each of FETs 2330-12 and 2330-13 dotted andconnected to wire 2330-14 which is connected to a second input of threeinput NAND gate 2350. NRAM™ 2310 provides configuration control bits C2to the gate of FET 2330-8 and C2′ to the gate of FET 2330-10. NRAM™ 2310provides configuration control logic bits C3 to the gate of FET 2330-12and C3′ to the gate of FET 2330-13.

NCLB 2300 also includes NRAM™ 2310 providing output C4 to one input oftwo input NAND gate 2345. The second input to NAND gate 2345 is suppliedby the output of NOR gate 2340. NRAM™ 2310 output C5 is connected to thethird input of three input NAND gate 2350. The outputs of two input NAND2345 and three input NAND 2350 drive the two inputs to NOR gate 2355.The output of two input NOR gate 2355 drives the input of tristateinverter 2360. The state of tristate inverter F is determined byconfiguration control bits C6 and C6′ which are provided by NRAM™ 2310.

FIG. 14B described further above illustrates eight nonvolatile circuitconfigurations (CKT CONFIG. #s 1-8) and the corresponding values of C0,C0′, . . . , C5 used to generate CKT CONFIG. #s 1-8 for NCLB 2300. FIG.14B gives an output F function based on inputs A and B and theconfiguration control logic states. Output F outputs logic values if theC6 state is a logic 1 and C6′ is a logic 0. However, if the C6 state isa logic 0 state and C6′ is a logic 1, then output F remains in tristatewith no defined value. FIG. 15 illustrates equivalent circuits 1500corresponding to CKT CONFIG. 1-8.

NPSM Function and Operation Using NRAM™s

An embodiment of nonvolatile nanotube programmable switch matrix NPSM2400 illustrated in FIG. 24 shows programmable switch matrix (PSM) 2410configured by nonvolatile NRAM™ 2420 outputs that provide configurationcontrol bits. Programmable switch matrix (PSM) 2410 is the same as PSM1610 described further above with respect to FIG. 16. NRAM™ 2420 maycorrespond to NRAM™ 2200 shown further above in FIG. 22A, NRAM™ 2250shown further above in FIG. 22B, or other NRAM™ configurations (notshown). Nonvolatile configuration control bits C1-C6 control theconfiguration of PSM 2410 as described above with respect PSM 1610 shownin FIG. 16. Configuration control bits C1-C6 drive the gates of FETsTS1, TS2, . . . , TS6, respectively, and determine the ON or OFF statesthese FETs.

As described further above with respect to FIG. 16, configurationcontrol bits (also referred to as configuration control logic states)programmed in NPSM 2400 may be used to form various routings betweenterminals A, B, C, and D. Exemplary interconnections achievable withNPSM 1600 are listed in Table 3 below.

TABLE 3 Number of FETs in ON State Possible Terminal CombinationsComments One AB, AC, AD, BC, BD, CD Independent paths Two AB & CD, AD &BC, AC & BD Independent paths Three ABC, ABD, ACD, BCD Shared paths FourABCD Shared paths

In a read operation, if NRAM™ 2420 corresponds to NRAM™ 2200 (FIG. 22A),then one set of configuration control bits is C1-C6 is provided to PSM2410 until the NRAM™ is reprogrammed. However, if NRAM™ 2420 correspondsto NRAM™ 2250 (FIG. 22B) then up to K different programmed configurationcontrol bit sets corresponding to C1-C6 may be read out and PSM 2410 mayassume multiple switch configuration by switching between multiplepre-programmed sets of bit states. The ability to rapidly change PSM2210 signal routing configurations as often as once per clock cycle,enables reconfigurable computing for example. If the logic function orrouting matrix to be programmed has the required configuration stored inNRAM™ arrays, then for relatively small NRAM™ arrays, configurationcontrol bits (true and complement) may be changed in cycle times of 150ps corresponding to clock frequencies of 6.7 GHz for example for a 90 nmtechnology node as described further above with respect to FIGS. 22A and22B. If the clock is stopped and power is removed, the NPSM 2400 routingconfiguration remains unchanged.

NFPGA Enabled Reconfigurable Computing Using NSRAMs

FPGA architectures are dominated by interconnects. FPGAs are thereforemuch more flexible in terms of the range of designs that can beimplemented and logic functions in the hundreds of thousands to millionsand tens-of-millions of equivalent logic gates may be realized. Inaddition, the added flexibility enables inclusion of higher-levelembedded functions such adders, multipliers, CPUs, and memory. The addedinterconnect (routing) flexibility of FPGAs also enables partialreconfiguration such that one portion of an FPGA chip may bereprogrammed while other portions are running FPGAs that can bereprogrammed while running may enable reconfigurable computing(reconfigurable systems) that reconfigure chip architecture to betterimplement logic tasks. The idea of reconfigurable computing is not new;however, implementation is limited by hardware capability andarchitecture and software. NRAM™s combined with FET switches and logiccircuits to form NFPGAs enable the hardware portion of reconfigurablecomputing by providing nonvolatile configuration control bits (alsoreferred to as nonvolatile configurable control logic states) that canchange logic functions and signal routing in real time during chipoperation and maintain such configurations in the absence of power asneeded resulting in nonvolatile globally adaptive and reconfigurablecapabilities in real time. Reconfigurable computing concepts aredescribed by G. G. Yen, “Autonomous Neural Control in Flexible SpaceStructures,” Chapter 93, pp. 1199-1202 in “The Industrial ElectronicsHandbook” edited by J. David Irwin, CRC Press LLC, 1997.

Reconfigurable computing involves both spatial and temporal partitions.NRAM™ 2250 as described further above with respect to FIG. 22B isdesigned to store K programmed combinations of configurable control bits(configurable control logic states) that can be read out at speeds asfast as 150 ps corresponding to 6.7 GHz for a 90 nm technology node forexample so NRAM™ 2250 may be used to reconfigure programmable logicblocks and programmable switch matrices in real time providing bothspatial and temporal partitions. In this example, NRAM™ 2250 enables thenonvolatile nanotube configurable logic block (NCLB) 2300 to be changedin as little time as one clock cycle (in pipeline mode) to support up toK logic configurations preprogrammed into NRAM™ 2250. Also, NRAM™ 2250enables the nonvolatile nanotube programmable switch matrix (NPSM) 2400to be reconfigured in as little time as one clock cycle (in pipelinemode) thereby rerouting signals in real time each cycle if needed.Nanotube bidirectional buffers described further above with respect toFIGS. 17A and 17B may also use NRAM™ configuration control bits (notshown) to redirect signal flow and change signal polarity, for example,in one cycle if needed. Hence, nonvolatile nanotube field programmablegate array (NFPGA) 2100 which is formed using various interconnectedNCLBs and NPSMs may be configured spatially and temporally within oneclock cycle when in a pipeline mode and over several cycles innon-pipelined operating mode.

Typically in reconfigurable computing, the number of spatial andtemporal changes needed is relatively small. Reprogramming NRAM™s mayonly be needed less than a few thousand times for example. In somecases, small NRAM™ memories are all that is needed so a small number ofconfiguration control bits may be preprogrammed. In the case of NCLB2300, K=8 (eight word lines) can accommodate the various configurationsillustrated in corresponding FIG. 14B. For NPSM 2400 variouscombinations of independent and shared routing configurations can beprogrammed as illustrated further above with respect to FIG. 24. If someNFPGA functions are not needed for certain computations for example,then power may be removed from these nonvolatile functions therebyeliminating standby power. Other NFPGA functions, embedded CPUs,memories, etc. May leverage these power savings by running faster athigher levels of power.

Embedded NRAM™ memories may be combined with FPGAs, CPUs and otherfunctions. In applications requiring fast cache operation, read andwrite times are essentially the same and may require cycle times of 150ps to support a 6.7 GHz clock rate for example. It may also be desirableto modify logic function and signal routing in one clock cycle withoutusing preprogrammed functions that may not cover all configurationcontrol bit requirements. In present generation NRAM™s write(erase/program) operations are significantly slower than readoperations. Hence, nanotube-based SRAM nonvolatile memories (NSRAMs) maybe desirable because high speed SRAM operation at read and write cycletimes of 150 ps (90 nm technology node) is enabled which supports aclock cycle of 6.7 GHz with the ability to save SRAM states in anonvolatile mode using nanotube-based nonvolatile switches as needed.

U.S. Pat. No. 7,245,520 to Bertin et al., incorporated herein byreference, illustrates NSRAM memory cell 2500 that may be used to formhigh speed (actually any speed range from low to high speed) NSRAMmemory by combining SRAM cell 2505 and a pair of nonvolatile nanotubeswitching elements 2530 and 2540. NSRAM memory cell 2500 includes aconventional SRAM cell formed by flip flop 2510 connected to word lineWL and bit lines BL1 and BL2 by select transistors FET T5 and FET T6,respectively, as described in more detail in U.S. Pat. No. 7,245,520which is hereby incorporated by reference. NSRAM memory cell 2500 alsoincludes nonvolatile nanotube switching elements 2530 and 2540 used asnonvolatile nanotube shadow devices that can store NSRAM memory cell2500 bit states in a nonvolatile mode prior to turn-off or loss of powerand also recall (restore) flip flop 2510 bit states when NSRAM cell 2500is reactivated (powered-up). Control wires V_(CNT) and V_(RL) are usedto control the switching of nonvolatile nanotube switching elements 2530and 2540 coupled to flip flop 2510 as shown in FIG. 25. A detaileddescription of NSRAM memory cell 2500 and its operation is described inthe incorporated U.S. Pat. No. 7,245,520 reference. The structure andoperation of nonvolatile nanotube switching elements 2530 and 2540 isdescribed in detail in U.S. Pat. Nos. 6,990,009, 7,339,401 and U.S.patent application Ser. No. 11/971,476, filed on Jan. 9, 2008, eachentitled “Nanotube-Based Switching Elements with Multiple Controls,” andU.S. Pat. No. 7,071,023 and U.S. patent application Ser. No. 11/449,969,filed on Jun. 9, 2006, each entitled “Nanotube Device Structure andMethods of Fabrication,” which are both hereby incorporated byreference.

An NSRAM memory may also be formed by replacing nonvolatile nanotubeswitching elements 2530 and 2540 in FIG. 25 with NRAM™ cells. Referringnow to FIG. 26, NRAM™ cells 2630 and 2640 (corresponding to nonvolatilenanotube switching elements 2530 and 2540 in FIG. 25) act as shadownonvolatile storage devices. Mode control transistors are added tosupport program and erase operations. NRAM™ cells 2630 and 2640correspond to NRAM™ cell 1100 shown in FIG. 11A. Flip flop 2610 shown inFIG. 26 corresponds to flip flop 2510 shown in FIG. 25.

One embodiment NSRAM cells 2600 may be combined in rows and columns toform NSRAM memories. NSRAM cells 2600 includes a conventional SRAM cellformed by flip flop 2610 connected to word line WL and bit lines BL1 andBL2 by select transistors FET T5 and FET T6, respectively. A firstterminal of NRAM™ cell 2630 select FET T7 is connected to a firstterminal of NV NT switch (or NV NT block) SW1 at common node N5. A firstterminal of mode select FET T9 is connected to common node N5. A secondterminal of FET T7 is connected to node N1 of flip flop 2610 shown inFIG. 26 which corresponds to flip flop 2510 in FIG. 25. Mode select lineV_(M1) is connected to the gate of FET T7 and controls the ON/OFF stateof FET T7. A second terminal of FET T9 is connected to a reference suchas ground (zero volts) and mode select line V_(M2) is connected to thegate of FET T9 and controls the ON/OFF state of FET T9. A secondterminal of NV NT switch SW1 is connected to erase/program/read selectline V_(EPR).

A first terminal of NRAM™ cell 2640 select FET T8 is connected to afirst terminal of NV NT switch (or NV NT block) SW2 at common node N6. Afirst terminal of mode select FET T10 is connected to common node N6. Asecond terminal of FET T8 is connected to node N2 of flip flop 2610shown in FIG. 26 which corresponds to flip flop 2510 in FIG. 25. Modeselect line V_(M1) is connected to the gate of FET T8 and controls theON/OFF state of FET T8. A second terminal of FET T10 is connected to areference such as ground (zero volts) and mode select line V_(M2) isconnected to the gate of FET T10 and controls the ON/OFF state of FETT10. A second terminal of NV NT switch SW2 is connected toerase/program/read select line V_(EPR).

An NSRAM memory (not shown) is formed in a conventional manner by acombination of rows and columns of NSRAM cells 2600 interconnected byshared approximately orthogonal word and bit lines. In operation, modeselect line V_(M1) is held at a low voltage such as ground and FET T7and FET T8 are in an OFF state and shadow devices pairs formed by NRAM™cell 2630 and 2640 are decoupled from flip flop 2610. Typically modeselect line V_(M2) is also held at ground turning FETs T9 and T10 OFFand program/erase/read line V_(EPR) is at a low voltage such as ground.SRAM cells such as cell 2605 operate in a volatile mode with memorycycle times as fast as 150 ps for a CMOS technology at a 90 nm node. IfSRAM power is to be removed or if power is about to be lost, then astore operation is performed in which FETs T7 and T8 are turned ON andthe logic state of flip flop 2610 is transferred and stored in NRAM™cell 2630 on NV NT switch (NV NT block) SW1 and a complementary state isstored in NRAM™ cell 2640 on NV NT switch (NV NT block) SW2. Power maythen be removed. The stored logic state may be recalled (restored)during power up in the following way. V_(EPR) may be held at ground ormay be ramped to a voltage such as V_(DD); SRAM cell 2605 voltage sourceis ramped to V_(DD). Flip flop 2610 assumes a state corresponding to thetrue and complement logic states stored in NRAM™ cells 2630 and 2640 andthe logic state of SRAM cell 2605 prior to power shutdown is restoredand SRAM memory operation resumes. Store and recall (restore) operationsare described in more detail in U.S. Pat. No. 7,245,520.

The integration of nanotube-based logic and memory functions asdescribed further above results in what may be referred to asinstant-OFF and instant-ON operations. The store operation that precedespower shut down may be performed in microseconds or milliseconds, forexample, resulting in what may be referred to as an instant-OFFoperation in which logic states and operating data are preserved in bynonvolatile nanotube switches or blocks. The recall (restore) operationmay be performed as part of a power-ON operation typically requiringmicroseconds or milliseconds, for example. Since logic states and dataare restored within a power-ON time interval and operational with thesystem initialized to pre-power-OFF logic states and data, such recall(restore) operations may be referred to as instant-ON.

An erase operation may be performed just prior to a store operation orat any time when FETs T7 and T8 are in an OFF state. During an eraseoperation, mode select line V_(M2) is set at a high voltage such as 2.5volts for example and FETs T9 and T10 are turned on grounding nodes N5and N6, respectively. Then, V_(EPR) applies one or more erase pulseswith an amplitude in the range of 5 to 7 volts and rise times in thenanosecond range for example to a second terminal of NV NT switches SW1and SW2 and switches SW1 and SW2 are switched to high resistance statessuch as 1 G Ohm or higher.

A program operation may be used store the logic content of flip flop2610 on switches SW1 and SW2 in a nonvolatile mode prior to the removalof power. FETs T9 and T10 are in an OFF state and NRAM™ cell 2630 selectFET T7 and NRAM™ cell 2640 select FET T8 are activated to an ON state.In this example, NV NT switches SW1 and SW2 are in a high resistance(OFF) state. Then, V_(EPR) applies one or more program pulses with anamplitude in the range of 3 to 5 volts and rise times in the microsecondrange for example to a second terminal of NV NT switches SW1 and SW2. Ifflip flop 2610 node N1 is at a low voltage and node N2 is at a highvoltage, then SW1 is programmed to a low resistance value such as 100 kOhms for example and SW2 remains in a high resistance state such as 1 GOhm. However, if flip flop 2610 node N1 is at a high voltage and node N2is at a low voltage, then SW1 is programmed remains at a resistancestate such as 1 G Ohms for example and SW2 switches to a low resistancestate such as 1 k Ohm.

In a program operation to store the state of flip flop 2610, flip flopsin some (or all) rows may transfer logic states to correspondingnonvolatile NRAM™ cells. However, program pulses may disturb some flipflops during the store operation. In order to minimize the risk ofdisturbing the state of flip flop 2610, transfer may be carried out oneword line at a time for a word line within a subset of word linescorresponding to a subset of latches. In this case, the logic state offlip flop 2610 is read out and bit line BL1 and BL2 are held at true andcomplement high/low or low/high values by corresponding senseamplifier/latches for each bit line pair such as bit lines BL1 and BL2.Select transistors FETs T5 and T6 are in an ON state, bit line BL2connected to node N4 holds node N1 at a low (or high) voltage and bitline BL1 connected to node N3 holds node N2 at a high (or low) voltage.In this way, program currents flow to bit lines BL1 or BL2 (whichever isat a low voltage) without disturbing the state of flip flop 2610. Forunselected rows, select transistors corresponding to select transistorFETs T5 and T6 are in an OFF state so that corresponding flip flops arenot disturbed.

In addition to fast programmable logic reconfiguration, NSRAMs may alsobe used to form high speed embedded nonvolatile caches used inconjunction with NFPGAs, CPUs, ASICs, analog, and other functions allintegrated on the same chip.

Nanotube Configurable Logic Blocks (NCLB) & Nanotube Programmable SwitchMatrix (NPSM) Using Nonvolatile NS/R-Controlled Select Circuit to FormNonvolatile Nanotube Configuration Control Register (NCCR)

Various nonvolatile nanotube configuration control registers (NCCRs) arecombined with CLB and PSM functions to form NCLB and NPSM buildingblocks that may be integrated to form NFPGA logic as described withrespect to FIGS. 19-26 illustrated further below. Nonvolatile nanotubeconfiguration control registers (NCCRs) are form using nonvolatilenanotube shift register (N-S/R) stages.

NFPGA Function and Operation Using Nonvolatile Nanotube ConfigurationControl Registers (NCCRs)

Since FPGA architectures are dominated by interconnects, it may beadvantageous to use configuration control registers to provideconfiguration control bits, typically one control bit per shift registerstage (also referred to as a shift register cell). This is because thenumber of shift register stages and therefore the number ofconfiguration control bits may be increased to any size while keepingthe number of inputs the same. In the case of NRAM™s for example, asarray size increases to provide more configuration control bits, decodersize increases requiring a larger number of inputs such as inputsillustrated in FIGS. 22A and 22B. Configuration control registers mayalso be used instead of nonvolatile nanotube select circuits illustratedin FIGS. 11B and 12A for example. Configuration control registers formedusing typical shift register (S/R) stages are volatile in operation;that is the logic states of the shift register stages are lost whenpower is lost or removed. In order to replace nonvolatile NRAM™s andnonvolatile nanotube select circuits described further above in variousNFPGA architectures, configuration control registers need to benonvolatile as well. U.S. Pat. No. 7,394,687 and U.S. patent applicationSer. No. 12/165,007, filed on Jun. 30, 2008, entitled “Non-VolatileShadow Latch Using a Nanotube Switch,” herein incorporated by referenceteaches the addition of NV NT switches to shift register stages (cells),typically one NV NT switch per stage, to form nonvolatile nanotube shiftregisters (NS/Rs) that are used to form nonvolatile nanotubeconfiguration control registers (NCCRs) which operate in a high speedvolatile mode at clock rates of 6.7 GHz at 2.5 volts for a CMOS 90 nmtechnology node for example, or at slower speeds but lower power at alower voltages such as 1 volt for example. Nonvolatile NCCRs can storeinformation in NV NT switches in the absence of power. When power isrestored, the high resistance or low resistance states of each NV NTswitch is used to restore individual corresponding NS/R stages to thelogic states prior to power shut-down or loss. The NS/R registersdescribed in U.S. Pat. No. 7,394,687 and U.S. patent application Ser.No. 12/165,007, filed on Jun. 30, 2008, entitled “Non-Volatile ShadowLatch Using a Nanotube Switch,” may provide nonvolatile configurationcontrol bits, one per stage, by connecting a wire directly to the outputof each output stage. Alternatively, an FET may be used as a transfergate to provide configuration control bits when the FET is in an ONstate.

It is desirable for individual NS/R stages to be as small as possiblefor greater layout density. A configuration control register of greaterdensity involving fewer numbers of FETs and interconnections per stagethan those described in U.S. Pat. No. 7,394,687 and U.S. patentapplication Ser. No. 12/165,007, filed on Jun. 30, 2008, entitled“Non-Volatile Shadow Latch Using a Nanotube Switch,” is shown in U.S.patent application Ser. No. 11/835,583, filed on Aug. 8, 2007, entitled“Latch Circuits and Operation Circuits Having Scalable NonvolatileNanotube Switches as Electronic Fuse Replacement Elements,” U.S. patentapplication Ser. No. 11/835,612, filed on Aug. 8, 2007, entitled“Nonvolatile Resistive Memories Having Scalable Two-Terminal NanotubeSwitches,” which is herein incorporated by reference and illustrated inFIG. 27. FIG. 27 corresponds to similar configuration control registersdescribed in US Pat. Re. 34,363.

FIG. 27 illustrates a schematic representation of a configurationcontrol register 2700 showing two stages of a multistage shift register.Although configuration control register 2700 shows two shift registercells, a configuration control register contains as many cells asrequired to configure the logic element. For example, if sevenconfiguration control bits (logic states) are required as illustrated inFIG. 23, then a seven stage configuration control register is used; ifsix configuration control bits (logical states) are required asillustrated in FIG. 24, then a six stage configuration control registeris used. A basic shift register cell includes transfer device 2712-1 inseries with inverter INV-1′, in series with transfer device 2716-1 whichis in series with inverter INV-1. The output Q1 of inverter INV-1 is fedback to the input of inverter INV-1′ through transfer device 2714-1enabling shift register CELL-2710-1 (shift register stage 1) to store alogic state as long as a power source is maintained (volatile shiftregister operation) to configuration control register 2700 and the HOLDvoltage is held high. The output Q1 of inverter INV-1 also connects tothe input of shift register CELL-2710-2, which is identical to shiftregister cell 1, and also connects to one terminal of transfer device2718-1. The output Q1′ of inverter INV-1′ connects to the input oftransfer device 2716-1. Two non-overlapping clocks Ψ1 and Ψ2 connect tocontrol gates of transfer devices 2712-1 and 2716-1, respectively, andto corresponding transfer devices in other shift register cells.Transfer device 2714-1 and corresponding devices in other cells enableor disable the feedback path between INV-1 output and INV-1′ inputdepending on the state of the HOLD input. Desired configuration controlbit (logic state) data is transmitted to configuration control register2700 by a LOGIC INPUT signal until each shift register cell (or stage)such as shift register CELL-2710-1 and CELL-2710-2 store the desired bit(logic state). Then APPLY control input is activated, and outputs Q1 andQ2 supply outputs configuration control bits such as C1 and C2 that maybe applied to reconfigurable logic functions such as illustrated in FIG.23 and programmable switch matrices such as illustrated in FIG. 24.Outputs Q2 and Q2′ in shift register CELL-2710-2 corresponds to outputsQ1 and Q1′ in shift register CELL-2710-1, respectively, describedfurther above.

In operation, the entire configuration control register 2700 may be setto a high or low voltage by setting Ψ1 and Ψ2 voltage high and HOLDvoltage low. Alternatively, with HOLD set at a high voltage, clocks Ψ1and Ψ2 may be used to transfer a logic pattern of 1's and 0' s into theshift register to store desired bit (logic states) in each of the shiftregister stages. Enough time must be allowed for the input signal LOGICINPUT to propagate the entire length of configuration control register2700. At that point in time, APPLY may transition to a positive voltageand outputs Q1 and Q2 supply configuration control bits (logic states)C1 and C2 that may be applied to reconfigurable logic functions such asillustrated in FIG. 23 and programmable switch matrices such asillustrated in FIG. 24.

It is desirable to have nonvolatile configuration control registers forNFPGA applications. One approach is to use the nonvolatile shiftregisters described in U.S. Pat. No. 7,394,687 and U.S. patentapplication Ser. No. 12/165,007, filed on Jun. 30, 2008, entitled“Non-Volatile Shadow Latch Using a Nanotube Switch.” Such nonvolatileshift registers are compatible with high speed operation and may also beused to hold logic states when power is removed or lost and then logicstates recalled (restored) when power is restored as described in U.S.Pat. No. 7,394,687 and U.S. patent application Ser. No. 12/165,007,filed on Jun. 30, 2008, entitled “Non-Volatile Shadow Latch Using aNanotube Switch.” However, since in some NFPGA architectures it isdesirable for individual NS/R stages to be as small as possible forgreater layout density, adding a coupling circuit and one NV NT switch(or NV NT block) to each stage of a configuration control register thatuses a fewer number of FETs and interconnections per stage than thosedescribed in U.S. Pat. No. 7,394,687 and U.S. patent application Ser.No. 12/165,007, filed on Jun. 30, 2008, entitled “Non-Volatile ShadowLatch Using a Nanotube Switch” is desirable. FIG. 28 illustratesnonvolatile nanotube configuration control register (NCCR) 2800 formedusing two NS/R stages in which one coupling circuit per stage and one NVNT switch (or NV NT block) per stage is added to configuration controlregister 2700 illustrated in FIG. 27.

FIGS. 28A-28C illustrate an embodiment of a two stage nonvolatilenanotube configuration control register (NCCR) 2800 formed usingnonvolatile nanotube shift register (NS/R) stages 2805-1 and 2805-2.NS/R stage 2805-1 includes CELL-2810-1 which corresponds to CELL-2710-1in FIG. 27 with NV NT switch (or NV NT block) 2820-1 coupled toCELL-2810-1 by coupling circuit 2830-1. Optional complementary outputsC1′ and C2′ are included since the outputs of inverters INV-1 and INV-1′are complementary. However, complementary outputs may instead begenerated from a single output such as C1 by adding an inverter to theoutput C1 as illustrated in FIG. 22A for example. NS/R stage 2805-2,with input driven by the output of NS/R stage 2805-1, includesCELL-2810-2 which corresponds to CELL-2710-2 in FIG. 27 with NV NTswitch (or NV NT block) 2820-2 coupled to CELL-2810-2 by couplingcircuit 2830-2. NS\R stages 2805-1 and 2805-2 are identical so the NS\Rstage 2805-1 description applied to NS\R stage 2805-2 as well or to anyadditional stages (not shown) that may be added. NV NT switch 2820-1operation corresponds to the operation of NV NT switch 1110 illustratedin FIG. 11A or NV NT switch NT00 illustrated in FIG. 19.

The CELL-2810-1 schematic and operation correspond to CELL-2710-1schematic and operation described further above with respect to FIG. 27.Restore FET 2840 ON and OFF states are controlled by a restore voltage(pulse) applied to the gate of restore FET 2840 by wire 2842 which alsocontrols other restore FET devices. A first terminal of restore FET 2840is connected to node N1 of CELL-2810-1 by wire 2845. Restore FET 2840 isactivated (turned ON) during a recall (restore operation) and is used totransfer the stored high or low resistance state corresponding to a bit(logic) state to CELL-2810-1. A second terminal of restore FET 2840 isconnected to terminal T1 of NV NT switch 2820-1. Terminal T2 of NV NTswitch 2820-1 is connected to common wire 2860 which supplies erase,program, or read pulses VE/P/R to NV NT switch 2820-1 and other NV NTswitches. Erase/program FET 2850 ON and OFF states are controlled by anerase/program voltage (pulse) applied to the gate of erase/program FET2850 by wire 2852 which also controls other erase/program FET devices.Erase/program FET 2850 has a first terminal connected to NV NT switchterminal T1 and a second terminal to common node N2 which is alsoconnected to a first terminal of FET 2855. A second terminal of FET 2855is connected to a reference voltage such as ground. The gate of FET 2855is connected to output Q1 of CELL-2810-1 by wire 2858. If Q1 is at ahigh voltage such as 2.5 volts for example, then FET 2855 is ON and nodeN2 is at ground. However, if Q1 is a low voltage such as ground (zerovolts) then FET 2855 is OFF and there is no continuous path between nodeN2 and ground. The ON or OFF state of FET 2855 determines whether NV NTswitch 2820-1 is programmed to a high or low resistance state which isthen stored in a nonvolatile mode.

In operation, NV NT switches such as NV NT switch 2820-1 are in ON orlow resistance state as fabricated although some process methods may beused that result in normally OFF states after fabrication as describedwith respect to U.S. Patent Application No. 61/074,241, filed on Jun.20, 2008, entitled “NRAM Arrays with Nanotube Blocks, Nanotube Traces,and Nanotube Planes and Methods of Making Same.” NV NT switch 2820-1acts as a shadow nonvolatile storage device which is only activated in astore (save) operation or in a recall (restore) operation. The operationof nonvolatile nanotube configuration control register (NCCR) 2800 issimilar to operation of nonvolatile nanotube registers described withrespect to U.S. Pat. No. 7,394,687 and U.S. patent application Ser. No.12/165,007, filed on Jun. 30, 2008, entitled “Non-Volatile Shadow LatchUsing a Nanotube Switch,” and corresponding NV NT switches described inU.S. patent application Ser. No. 11/280,786, filed on Nov. 15, 2005,entitled “Two-Terminal Nanotube Devices and Systems and Methods ofMaking,” U.S. patent application Ser. No. 11/274,967, filed on Nov. 15,2005, entitled “Memory Arrays Using Nanotube Articles withReprogrammable Resistance U.S. patent application Ser. No. 11/835,583,filed on Aug. 8, 2007, entitled “Latch Circuits and Operation CircuitsHaving Scalable Nonvolatile Nanotube Switches as Electronic FuseReplacement Elements,” U.S. patent application Ser. No. 11/835,612,filed on Aug. 8, 2007, entitled “Nonvolatile Resistive Memories HavingScalable Two-Terminal Nanotube Switches,” U.S. patent application Ser.Nos. 11/835,651, 11/835,759, 11/835,845, 11/835,852, 11/835,856,11/835,865, each filed on Aug. 8, 2007, entitled “Nonvolatile NanotubeDiodes and Nonvolatile Nanotube Blocks and Systems Using Same andMethods of Making Same,” and U.S. patent application Ser. No.11/835,613, filed on Aug. 8, 2007, entitled “Memory Elements and CrossPoint Switches and Arrays of Same Using Nonvolatile Nanotube Blocks,” aswell as the operation of switch 1110 in FIG. 11A, switches 1155 and 1160illustrated in FIG. 11B and switch NT00 illustrated in FIG. 19 forexample.

Various operating modes may be used. In this example, NV NT switchessuch as NV NT switch 2820-1 are assumed to be ON as fabricated. Sofirst, an erase operation is performed on NV NT switches such as NV NTswitch 2820-1 resulting in a transition from an ON low resistance statesuch as 100 k Ohms for example to an OFF high resistance state of 1 GOhm or higher. In an erase operation, the HOLD voltage is set to a lowvoltage such as ground and Ψ1 and Ψ2 voltages are set to a high voltagesuch as 2.5 volts for example. With LOGIC INPUT held at a high voltagesuch as 2.5 volts Q1 is held at 2.5 volts and turns erase/program FET2855 ON. ERASE/PROGRAM voltage is set to a high voltage such as 2.5volts for example and erase/program FET 2850 is turned ON establishing aconductive path between NV NT switch terminal T1 and ground. RESTOREvoltage is held at a low voltage such as ground so that restore FET 2840is OFF. Then, VE/P/R provides erase pulses to node T2 of NV NT switch2820-1. One or more pulses with voltages in the 5 to 7 volt range andrise times in the nanosecond range may be used for example. NV NT switch2820-1 transitions from an ON state to an OFF state (low to highresistance state). Corresponding NV NT switch 2820-2 also transitions toan OFF state as illustrated by nonvolatile nanotube configurationcontrol register (NCCR) 2800′ in FIG. 28B.

Alternatively, another FET (not shown) may have a first terminalconnected to node N2, a second terminal connected to a voltage sourcewhich may be pulsed or may be at ground, and a gate controlled by asecond erase/program line. In this way, an erase operation for example,may be performed independently of CELL-2810-1. Various coupling circuitexamples are described in U.S. Pat. No. 7,394,687 and U.S. patentapplication Ser. No. 12/165,007, filed on Jun. 30, 2008, entitled“Non-Volatile Shadow Latch Using a Nanotube Switch.”

NCCR 2800′ is the same circuit as NCCR 2800 except that NV NT switches2820-1 and 2820-2 are in OFF or high resistance states. CELL-2810-1 andCELL-2810-2 and other stages (not shown) may operate in a volatile modewhenever coupling circuits 2830-1 and 2830-2 decouple corresponding NVNT switches 2820-1 and 2820-2 from CELL-2810-1 and CELL-2810-2,respectively, regardless of the low or high resistance states of NV NTswitches. Coupling circuit 2830-1, which is the same as coupling circuit2830-2, maintains an OFF state by keeping restore FET 2840 anderase/program FET 2850 each in an OFF state with low RESTORE andERASE/PROGRAM voltages, respectively. Nonvolatile nanotube configurationcontrol registers are operated in a volatile mode with high voltagessuch as 2.5 volts supplied to inverters INV-1 and INV-1′ for example.

In a store (save) operation, NV NT switches are programmed from a highresistance state to a low resistance state or left in a high resistancestate. With restore FET 2840 in an OFF state, erase/program FET 2850 isturned ON. If FET 2855 is an ON state because Q1 is at a high voltagesuch 2.5 volts, then a continuous path exists between NV NT switch2820-1 terminal T1 and ground. If one or more programming pulses VE/P/Rof 3-5 volts and microsecond rise times are applied to terminal T2 of NVNT switch 2820-1, then NV NT switch 2820-1 transitions from a highresistance state such as 1 G Ohm to a low resistance state such as 100 kOhms for example. However, if FET 2855 is OFF because Q1 is at a lowvoltage such as ground, then there is no path between NV NT 2820-1terminal T1 and ground and NV NT switch 2820-1 remains in a highresistance state. After the state of NV NT switch 2820-1 and other NV NTswitches such as NV NT switch 2820-1 have been programmed, then powermay be removed and the logic state of CELL-2810-1 and CELL-2810-2 arepreserved in a nonvolatile mode as corresponding high or low resistancestates. In this example, nonvolatile nanotube configuration controlregister 2800″ shows NV NT switch 2820-1 in a high resistance state andNV NT switch 2820-2 programmed to a low resistance state as illustratedin FIG. 28C. Note that NCCR 2800, NCCR 2800′, and NCCR 2800″ allcorrespond to the same circuit with NV NT switches in variouscombinations of low (ON) and high (OFF) resistance states.

In a recall (restore) operation, erase/program FET 2850 is held in OFFstate. A voltage is applied to CELL-2810-1 (typically, a voltage sourceis ramped to 2.5 volts for example). With HOLD, Ψ1, and Ψ2 at highvoltages such as 2.5 volts and a LOGIC INPUT of zero volts, node N1 isheld at ground by output Q1 of INV-1. Then Ψ1 voltage transitions to alow voltage state and decouples all individual register stages such asCELL-2810-1 from one another and voltage. With VE/P/R havingtransitioned to a recall (restore) voltage value applied to wire 2860and to node T2, restore FET 2840 is turned ON and a conductive path isestablished between NV NT switch 2820-1 terminal T1 and CELL 2810-1 nodeN1. If NV NT switch 2820-1 is in a low resistance (ON) state, then nodeN1 is forced to a high voltage state such as 2.5 volts as does theoutput Q1 of INV-1. However, if NV NT switch 2820-1 is in a highresistance (OFF) state, then N1 remains at a low voltage. Restore FET2840 is turned OFF and the recall (restore) operation is finished. U.S.Pat. No. 7,394,687 and U.S. patent application Ser. No. 12/165,007,filed on Jun. 30, 2008, entitled “Non-Volatile Shadow Latch Using aNanotube Switch” provides various store (save) and recall (restore)examples.

NCLB Function and Operation Using Nonvolatile Nanotube ConfigurationControl Registers (NCCRs)

Nonvolatile nanotube configuration control registers (NCCBs) may be usedto generate nonvolatile configuration control bits (logic states) forNCLB functions. For example, a NCCB may be used instead of nonvolatilenanotube select circuits illustrated by NCLB 1400 shown in FIG. 14A.Also, a NCCB may used instead of NRAM™-based nonvolatile configurationcontrol bits (logic states) illustrated by NCLB 2300 shown in FIG. 23.

FIG. 29 illustrates an embodiment NCLB 2900 with nonvolatile nanotubeconfiguration control register (NCCB) 2905 generating nonvolatileconfiguration control bits (logic states) C0, C0′, . . . , C6 and C6′).NCLB 2900 uses seven NS/R stages CELL 2910-1, CELL 2910-2, . . . , CELL2910-7 to provide the required configuration control bits. The operationof NCCR 2900 corresponds to the operation described with respect to NCCR2800, 2800′, and 2800″ in FIGS. 28A-28C. Reconfigurable logic 2915 isthe same as shown in FIGS. 14 and 23 and described in detail furtherabove with respect to these figures. FIG. 14B shows logic configurationscorresponding to various configuration control bit combinations; andFIG. 15 illustrates equivalent circuits as described further above.

NPSM Function and Operation Using Nonvolatile Nanotube ConfigurationControl Registers (NCCRs)

Nonvolatile nanotube configuration control registers (NCCBs) may be usedto generate nonvolatile configuration control bits (logic states) forNPSM functions. For example, a NCCB may be used instead of nonvolatilenanotube select circuits illustrated by NPSM 1600 shown in FIG. 16.Also, a NCCB may used instead of NRAM™-based nonvolatile configurationcontrol bits (logic states) illustrated by NPSM 2400 shown in FIG. 24.

FIG. 30 illustrates an embodiment NPSM 3000 with nonvolatile nanotubeconfiguration control register (NCCB) 3005 generating nonvolatileconfiguration control bits (logic states) C1, C2, . . . , C6). NPSM 3000uses six NS/R stages CELL 3010-1, CELL 3010-2, . . . , CELL 3910-6 toprovide the required configuration control bits. The operation of NCCR3000 corresponds to the operation described with respect to NCCR 2800,2800′, and 2800″ in FIGS. 28A-28C. Programmable switch matrix 3015 isthe same as shown in FIGS. 16 and 24 and described in detail furtherabove with respect to these Figures.

INCORPORATED PATENT REFERENCES

The following commonly-owned patent references, referred to herein as“incorporated patent references,” describe various techniques forcreating nanotube elements (nanotube fabric articles and switches),e.g., creating and patterning nanotube fabrics, logic circuits formedtherefrom, devices and structures using nanotube articles and switches,etc. and are incorporated by reference in their entireties:

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No. 11/835,759, filed on Aug. 8,        2007, entitled NONVOLATILE NANOTUBE DIODES AND NONVOLATILE        NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING        SAME;    -   U.S. patent application Ser. No. 11/835,845, filed on Aug. 8,        2007, entitled NONVOLATILE NANOTUBE DIODES AND NONVOLATILE        NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING        SAME;    -   U.S. patent application Ser. No. 11/835,852, filed on Aug. 8,        2007, entitled NONVOLATILE NANOTUBE DIODES AND NONVOLATILE        NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING        SAME;    -   U.S. patent application Ser. No. 11/835,856, filed on Aug. 8,        2007, entitled NONVOLATILE NANOTUBE DIODES AND NONVOLATILE        NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING        SAME;    -   U.S. patent application Ser. No. 11/835,865, filed on Aug. 8,        2007, entitled NONVOLATILE NANOTUBE DIODES AND NONVOLATILE        NANOTUBE BLOCKS AND SYSTEMS USING SAME AND METHODS OF MAKING        SAME;    -   U.S. patent application Ser. No. 11/835,613, filed on Aug. 8,        2007, entitled MEMORY ELEMENTS AND CROSS POINT SWITCHES AND        ARRAYS OF SAME USING NONVOLATILE NANOTUBE BLOCKS;    -   U.S. Patent Application No. 61/039,204, filed on Mar. 25, 2008,        entitled CARBON NANOTUBE-BASED NEURAL NETWORKS AND METHODS OF        MAKING AND USING SAME;    -   U.S. Pat. No. 7,394,687, filed on Nov. 15, 2005, entitled        NON-VOLATILE SHADOW LATCH USING A NANOTUBE SWITCH;    -   U.S. patent application Ser. No. 12/165,007, filed on Jun. 30,        2008, entitled NON-VOLATILE SHADOW LATCH USING A NANOTUBE        SWITCH;    -   U.S. patent application Ser. No. 11/274,967, filed on Nov. 15,        2005, entitled MEMORY ARRAYS USING NANOTUBE ARTICLES WITH        REPROGRAMMABLE RESISTANCE;    -   U.S. Pat. No. 7,115,901, filed on Jun. 9, 2004, entitled        NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT DEVICES AND CIRCUITS        USING SAME AND METHODS OF FORMING SAME;    -   U.S. Pat. No. 7,268,044, filed on Oct. 2, 2006, entitled        NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT DEVICES AND CIRCUITS        USING SAME AND METHODS OF FORMING SAME;    -   U.S. patent application Ser. No. 11/731,946, filed on Apr. 2,        2007, entitled NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT        DEVICES AND CIRCUITS USING SAME AND METHODS OF FORMING SAME;    -   U.S. Pat. No. 6,982,903, filed on Jun. 9, 2004, entitled FIELD        EFFECT DEVICES HAVING A SOURCE CONTROLLED VIA A NANOTUBE        SWITCHING ELEMENT;    -   U.S. Pat. No. 7,280,394, filed on Jun. 9, 2004, entitled FIELD        EFFECT DEVICES HAVING A DRAIN CONTROLLED VIA A NANOTUBE        SWITCHING ELEMENT;    -   U.S. Pat. No. 7,211,854, filed on Jun. 9, 2004, entitled FIELD        EFFECT DEVICES HAVING A GATE CONTROLLED VIA A NANOTUBE SWITCHING        ELEMENT;    -   U.S. patent application Ser. No. 11/742,290, filed on Apr. 30,        2007, entitled FIELD EFFECT DEVICES HAVING A GATE CONTROLLED VIA        A NANOTUBE SWITCHING ELEMENT;    -   U.S. Pat. No. 7,301,802, filed on Jun. 9, 2004, entitled CIRCUIT        ARRAYS HAVING CELLS WITH COMBINATIONS OF TRANSISTORS AND        NANOTUBE SWITCHING ELEMENTS;    -   U.S. Pat. No. 7,112,493, filed on Jun. 9, 2004, entitled METHOD        OF MAKING NON-VOLATILE FIELD EFFECT DEVICES AND ARRAYS OF SAME;    -   U.S. patent application Ser. No. 11/527,127, filed on Sep. 26,        2006, entitled METHOD OF MAKING NON-VOLATILE FIELD EFFECT        DEVICES AND ARRAYS OF SAME;    -   U.S. Pat. No. 7,115,960, filed on Aug. 13, 2004, entitled        NANOTUBE-BASED SWITCHING ELEMENTS;    -   U.S. patent application Ser. No. 11/542,524, filed on Oct. 3,        2006, entitled NANOTUBE-BASED SWITCHING ELEMENTS;    -   U.S. Pat. No. 6,990,009, filed on Aug. 13, 2004, entitled        NANOTUBE-BASED SWITCHING ELEMENTS WITH MULTIPLE CONTROLS;    -   U.S. Pat. No. 7,339,401, filed on Aug. 4, 2005, entitled        NANOTUBE-BASED SWITCHING ELEMENTS WITH MULTIPLE CONTROLS;    -   U.S. patent application Ser. No. 11/971,476, filed on Jan. 9,        2008, entitled NANOTUBE-BASED SWITCHING ELEMENTS WITH MULTIPLE        CONTROLS;    -   U.S. Pat. No. 7,228,970, filed on Sep. 24, 2001, entitled        INTEGRATED NANOTUBE AND FIELD EFFECT SWITCHING DEVICE;    -   U.S. patent application Ser. No. 11/929,076, filed on Oct. 30,        2007, entitled INTEGRATED NANOTUBE AND FIELD EFFECT SWITCHING        DEVICE;    -   U.S. Pat. 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The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The presentembodiments are therefore to be considered in respects as illustrativeand not restrictive.

1. A programmable nonvolatile nanotube select circuit comprising: afirst two-terminal nonvolatile nanotube switch and a second two-terminalnonvolatile nanotube switch, wherein each of the first and secondtwo-terminal nonvolatile nanotube switches comprises a first terminaland a second terminal, wherein the first and second terminals of thefirst nonvolatile nanotube switch are in contact with opposite ends of afirst nanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element, and the second terminal of the firstnonvolatile nanotube switch and the second terminal of the secondnonvolatile nanotube switch share a common node; and a field effecttransistor (FET) having a drain region, a source region, a channelregion positioned between the drain and source regions, and a gate nodein proximity to the channel region, wherein the gate node modulates theconductivity of the channel region and wherein the drain region of theFET is electrically coupled to the common node.
 2. The programmablenonvolatile nanotube select circuit of claim 1 wherein the field effecttransistor is a nanotube field effect transistor.
 3. A programmablenanotube logic circuit comprising: a programmable nonvolatile nanotubeselect circuit comprising: a first two-terminal nonvolatile nanotubeswitch and a second two-terminal nonvolatile nanotube switch, whereineach of the first and second two-terminal nonvolatile nanotube switchescomprises a first terminal and a second terminal, wherein the first andsecond terminals of the first nonvolatile nanotube switch are in contactwith opposite ends of a first nanotube element and the first and secondterminals of the second nonvolatile nanotube switch are in contact withopposite ends of a second nanotube element, and the second terminal ofthe first nonvolatile nanotube switch and the second terminal of thesecond nonvolatile nanotube switch share a common node; and a fieldeffect transistor (FET) having a drain region, a source region, achannel region positioned between the drain and source regions, and agate node in proximity to the channel region, wherein the gate nodemodulates the conductivity of the channel region and wherein the drainregion of the FET is electrically coupled to the common node; a Booleanlogic circuit comprising at least one input and an output wherein afirst input of the at least one inputs is electrically coupled to thecommon node of the programmable nonvolatile nanotube select circuit. 4.A programmable nanotube circuit comprising: a programmable nonvolatilenanotube select circuit comprising: a first two-terminal nonvolatilenanotube switch and a second two-terminal nonvolatile nanotube switch,wherein each of the first and second two-terminal nonvolatile nanotubeswitches comprises a first terminal and a second terminal, wherein thefirst and second terminals of the first nonvolatile nanotube switch arein contact with opposite ends of a first nanotube element and the firstand second terminals of the second nonvolatile nanotube switch are incontact with opposite ends of a second nanotube element, and the secondterminal of the first nonvolatile nanotube switch and the secondterminal of the second nonvolatile nanotube switch share a common node;and a field effect transistor (FET) having a drain region, a sourceregion, a channel region positioned between the drain and sourceregions, and a gate node in proximity to the channel region, wherein thegate node modulates the conductivity of the channel region and whereinthe drain region of the FET is electrically coupled to the common node;a transfer device comprising an input, an output, and a control terminalwherein the control terminal is electrically coupled to the common nodeof the programmable nonvolatile nanotube select circuit to enabletransfer of a signal at the input of the transfer device to the outputof the transfer device.
 5. A nonvolatile nanotube configurable logiccircuit comprising: a first, second and third plurality of inputterminals and at least an output terminal; a plurality of programmablenonvolatile nanotube select circuits, each nonvolatile nanotube selectcircuit comprising: a first two-terminal nonvolatile nanotube switch anda second two-terminal nonvolatile nanotube switch, wherein each of thefirst and second two-terminal nonvolatile nanotube switches comprises afirst terminal and a second terminal, wherein the first and secondterminals of the first nonvolatile nanotube switch are in contact withopposite ends of a first nanotube element and the first and secondterminals of the second nonvolatile nanotube switch are in contact withopposite ends of a second nanotube element, and the second terminal ofthe first nonvolatile nanotube switch and the second terminal of thesecond nonvolatile nanotube switch share a common node; and a fieldeffect transistor (FET) having a drain region, a source region, achannel region positioned between the drain and source regions, and agate node in proximity to the channel region, wherein the gate nodemodulates the conductivity of the channel region and wherein the drainregion of the FET is electrically coupled to the common node; whereinthe first plurality of input terminals is electrically coupled to thefirst terminals of the nonvolatile nanotube switches and the secondplurality of terminals are electrically coupled to the gate regions ofthe nonvolatile nanotube switches; a first plurality of transfer deviceselectrically coupled to the signals on the third plurality of inputterminals, the first plurality of transfer devices also electricallycoupled to the signals on the common nodes of the nonvolatile nanotubeswitches; a second plurality of transfer devices electrically coupled tothe complementary signals on the third plurality of input terminals, thesecond plurality of transfer devices also electrically coupled to thecomplementary signals on the common nodes of the nonvolatile nanotubeswitches; and wherein the signals on the first plurality of inputterminals are able to configure the first plurality of transfer devicesand the second plurality of transfer devices to implement a plurality ofBoolean logic functions at the output terminal.
 6. A nonvolatilenanotube programmable switch matrix comprising: a first, second andthird plurality of terminals; a plurality of programmable nonvolatilenanotube select circuits, each nonvolatile nanotube select circuitcomprising: a first two-terminal nonvolatile nanotube switch and asecond two-terminal nonvolatile nanotube switch, wherein each of thefirst and second two-terminal nonvolatile nanotube switches comprises afirst terminal and a second terminal, wherein the first and secondterminals of the first nonvolatile nanotube switch are in contact withopposite ends of a first nanotube element and the first and secondterminals of the second nonvolatile nanotube switch are in contact withopposite ends of a second nanotube element, and the second terminal ofthe first nonvolatile nanotube switch and the second terminal of thesecond nonvolatile nanotube switch share a common node; and a fieldeffect transistor (FET) having a drain region, a source region, achannel region positioned between the drain and source regions, and agate node in proximity to the channel region, wherein the gate nodemodulates the conductivity of the channel region and wherein the drainregion of the FET is electrically coupled to the common node; whereinthe first plurality of terminals are electrically coupled to the firstterminals of the nonvolatile nanotube switches and the second pluralityof terminals are electrically coupled to the gate regions of thenonvolatile nanotube switches; and a plurality of transfer deviceselectrically coupled to the common nodes of the programmable nonvolatilenanotube select circuits, the plurality of transfer devices alsoelectrically coupled to the third plurality of terminals so as toprovide routing between any two terminals of the third plurality ofterminals.
 7. A nanotube bi-directional buffer circuit comprising: afirst and second bi-directional terminals; a first and second buffers,each buffer comprising an input, an output, and a transfer device; aprogrammable nonvolatile select circuit comprising: a first two-terminalnonvolatile nanotube switch and a second two-terminal nonvolatilenanotube switch, wherein each of the first and second two-terminalnonvolatile nanotube switches comprises a first terminal and a secondterminal, wherein the first and second terminals of the firstnonvolatile nanotube switch are in contact with opposite ends of a firstnanotube element and the first and second terminals of the secondnonvolatile nanotube switch are in contact with opposite ends of asecond nanotube element, and the second terminal of the firstnonvolatile nanotube switch and the second terminal of the secondnonvolatile nanotube switch share a common node; and a field effecttransistor (FET) having a drain region, a source region, a channelregion positioned between the drain and source regions, and a gate nodein proximity to the channel region, wherein the gate node modulates theconductivity of the channel region and wherein the drain region of theFET is electrically coupled to the common node; wherein the firstbi-directional terminal is electrically coupled to the input of thefirst buffer and the output of the second buffer; wherein the secondbi-directional terminal is electrically coupled to the input of thesecond buffer and the output of the first buffer; wherein the signal onthe common node of the programmable nonvolatile nanotube select circuitis electrically coupled to the transfer device of the first buffer toenable signal flow from the second bi-directional terminal to the firstbi-directional terminal; wherein the complementary signal on the commonnode of the programmable nonvolatile nanotube select circuit iselectrically coupled to the transfer device of the second buffer toenable signal flow from the first bi-directional terminal to the secondbi-directional terminal.